Functional Description

The DDR interface block has three input pins for reset control:

Master reset (active low)
Sequencer reset (active high)
Sequencer start (active high)

Note: These reset pins are not available if you are using I²C calibration.

You provide a single reset signal and a clock to the DDR Hard Memory Controller-Reset core, and it generates outputs that drive these reset pins. Optionally, the code generates a status signal. Your system can monitor the status to know when the reset and DDR re-initialization completes and that read/write operations to the DDR AXI interfaces can resume.

The core contains one parameter, FREQ, which should correspond to the clk signal's frequency.

Note: You do not need to reset the DDR block when the FPGA configures or when the FPGA initially goes into user mode. The DDR reset and initialization is triggered automatically during configuration.

Figure 1. DDR Hard Memory Controller-Reset Core Block Diagram