AXI Interconnect Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example designs target the Titanium Ti60 F225 Development Board. The design implements an AXI Interconnect in the FPGA and demonstrates a single master port access to eight different slave ports. The read and write data is routed by the AXI Interconnect core according to addresses assigned.

Figure 1. AXI Interconnect Example Design

The master issues eight 128-burst of AXI write data each targeting 8 different slaves. Each slave consists of 128-depth data FIFO making each data transaction to fill up the available FIFO. The master issues read operation to all slaves. Then the master compares read data with the write data from each slave accordingly. The development board LEDs output the following:

Table 1. Example Design Output
Output	Result	Description
LED D16 Blue	Test Done	Indicates the test is completed.
LED D16 Green	Test Pass	Indicates the written and read data are matched.
LED D16 Red	Test Fail	Indicates the written and read data are not matched.

Table 2. Slave Ports Address Range
Base Address	Address Width	Base Address Bits Value	Address Start	Address End
0x00000000	28	0x0	0x00000000	0x0FFFFFFF
0x10000000	24	0x10	0x10000000	0x10FFFFFF
0x11000000	12	0x11000	0x11000000	0x11000FFF
0x11100000	20	0x111	0x11100000	0x111FFFFF
0x20000000	28	0x2	0x20000000	0x2FFFFFFF
0x30000000	28	0x3	0x30000000	0x3FFFFFFF
0x40000000	24	0x40	0x40000000	0x40FFFFFF
0x41000000	20	0x410	0x41000000	0x410FFFFF