AXI Interconnect Operations

The following two waveforms illustrate a 2-to-1 interconnect example using fixed priority arbitration mode. There are three requests from two AXI master ports. The AXI Interconnect core grants read operation from port 1 (s_axi_arvalid[1]) because:
  • Port 1 has a higher index (MSB)
  • A read operation has a higher priority than a write operation

The ready signal of the address channel (s_axi_arready[1]) assertion indicates the request has been accepted. There is one clock cycle latency for the read request to be present on the AXI interconnect output.

Figure 1. Fixed Priority Arbitration 2-to-1 Interconnect Example Waveform (Request)

Read operations, there is one clock cycle latency for the data to be present on the AXI interconnect input.

Figure 2. Fixed Priority Arbitration 2-to-1 Interconnect Example Waveform (Read)

The following waveform illustrates the AXI interconnect of a 1-to-8 operation. The AXI interconnect decodes the slave destination from the write/read address channel and routes the transaction to the corresponding destination. For example, each of the connected slaves has a 12-bit address range. Address ‘h4000 indicates that the transaction request is targeting slave port 4.

Figure 3. 1-to-8 Interconnect Example Waveform

The following waveform illustrates a transaction address request with an invalid range. Each of the connected slaves has a 12-bit address range. There are eight destination slaves configured in the AXI interconnect where the valid decoded address range is 0h0 to 0h7fff. However, the master side is driving a transaction address to hE000, which is out of the valid address range. The AXI Interconnect core denies the transaction by returning the decoder error.

Figure 4. Invalid Transaction Address Example Waveform