Ports

Note: M represents the number of AXI master ports while S represents the number of AXI slave ports.

Table 1. Global
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
clk	Input				Clock.
rst_n	Input				Active low asynchronous reset.

Table 2. Write Address Channel (Slave)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
s_axi_awvalid[S-1:0]	Input				Write address channel valid.
s_axi_awaddr[S*ADDR_WIDTH-1:0]	Input				Write address channel address.
s_axi_awprot[S*3-1:0]	Input				Write address channel protect.
s_axi_awid[S*ID_WIDTH-1:0]	Input			–	Write address channel transaction ID.
s_axi_awburst[S*2-1:0]	Input			–	Write address channel burst type.
s_axi_awlen[S*8-1:0]	Input			–	Write address channel burst length.
s_axi_awsize[S*3-1:0]	Input			–	Write address channel transfer size.
s_axi_awcache[S*4-1:0]	Input	–		–	Write address channel cache encoding.
s_axi_awqos[S*4-1:0]	Input	–		–	Write address channel Quality of Service (QoS).
s_axi_awuser[S*USER_WIDTH-1:0]	Input	–		–	Write address channel user-defined signals.
s_axi_awlock[S*2-1:0]	Input		–	–	Write address channel locked transaction. Tie to `0` when using AXI Lite.
s_axi_awready[S-1:0]	Output				Write address channel ready.

Table 3. Write Data Channel (Slave)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
s_axi_wvalid[S-1:0]	Input				Write channel valid.
s_axi_wdata[S*DATA_WIDTH-1:0]	Input				Write channel data.
s_axi_wstrb[S*STRB_WIDTH-1:0]	Input				Write channel strobe (Single bit represents data byte).
s_axi_wlast[S-1:0]	Input			–	Write channel last data beat. Tie to `1` when using AXI Lite.
s_axi_wuser[S*USER_WIDTH-1:0]	Input	–		–	Write channel user-defined signals.
s_axi_wid[S*ID_WIDTH-1:0]	Input		–	–	Write channel transaction ID. Tie to `0` when using AXI Lite.
s_axi_wready[S-1:0]	Output				Write channel ready.

Table 4. Write Response Channel (Slave)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
s_axi_bready[S-1:0]	Input				Write response channel ready.
s_axi_bresp[S*2-1:0]	Output				Write response channel response.
s_axi_bvalid[S-1:0]	Output				Write response channel valid.
s_axi_bid[S*ID_WIDTH-1:0]	Output			–	Write response channel transaction ID.
s_axi_buser[S*USER_WIDTH-1:0]	Output	–		–	Write response channel user-defined ID.

Table 5. Read Address Channel (Slave)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
s_axi_arvalid[S-1:0]	Input				Read address channel valid.
s_axi_araddr[S*ADDR_WIDTH-1:0]	Input				Read address channel address.
s_axi_arprot[S*3-1:0]	Input				Read address channel protect.
s_axi_arid[S*ID_WIDTH-1:0]	Input			–	Read address channel transaction ID.
s_axi_arburst[S*2-1:0]	Input			–	Read address channel burst type.
s_axi_arlen[S*8-1:0]	Input			–	Read address channel burst length.
s_axi_arsize[S*3-1:0]	Input			–	Read address channel transfer size.
s_axi_arcache[S*4-1:0]	Input	–		–	Read address channel cache encoding.
s_axi_arqos[S*4-1:0]	Input	–		–	Read address channel QoS.
s_axi_aruser[S*USER_WIDTH-1:0]	Input	–		–	Read address channel user-defined signals.
s_axi_arlock[S*2-1:0]	Input		–	–	Read address channel locked transaction.
s_axi_arready[S-1:0]	Output				Read address channel ready.

Table 6. Read Data Channel (Slave)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
s_axi_rready[S-1:0]	Input				Read data channel ready.
s_axi_rid[S*ID_WIDTH-1:0]	Output			–	Read data channel transaction ID.
s_axi_rdata[S*DATA_WIDTH-1:0]	Output				Read data channel data.
s_axi_rresp[S*2-1:0]	Output				Read data channel response.
s_axi_rvalid[S-1:0]	Output				Read data channel valid.
s_axi_rlast[S-1:0]	Output			–	Read data channel last data beat.
s_axi_ruser[S*USER_WIDTH-1:0]	Output	–		–	Read data user-defined channel.

Table 7. Write Address Channel (Master)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
m_axi_awvalid[M-1:0]	Output				Write address channel valid.
m_axi_awaddr[M*ADDR_WIDTH-1:0]	Output				Write address channel address.
m_axi_awprot[M*3-1:0]	Output				Write address channel protect.
m_axi_awid[M*ID_WIDTH-1:0]	Output			–	Write address channel transaction ID.
m_axi_awburst[M*2-1:0]	Output			–	Write address channel burst type.
m_axi_awlen[M*8-1:0]	Output			–	Write address channel burst length.
m_axi_awsize[M*3-1:0]	Output			–	Write address channel transfer size.
m_axi_awcache[M*4-1:0]	Output	–		–	Write address channel cache encoding.
m_axi_awqos[M*4-1:0]	Output	–		–	Write address channel QoS.
m_axi_awuser[M*USER_WIDTH-1:0]	Output	–		–	Write address channel user-defined signals.
m_axi_awlock[M*2-1:0]	Output		–	–	Write address channel locked transaction.
m_axi_awready[M-1:0]	Input				Write address channel ready.

Table 8. Write Data Channel (Master)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
m_axi_wvalid[M-1:0]	Output				Write channel valid.
m_axi_wdata[M*DATA_WIDTH-1:0]	Output				Write channel data.
m_axi_wstrb[M*STRB_WIDTH-1:0]	Output				Write channel strobe (single bit represents data byte).
m_axi_wlast[M-1:0]	Output			–	Write channel last data beat.
m_axi_wuser[M*USER_WIDTH-1:0]	Output	–		–	Write channel user-defined signals.
m_axi_wid[M*ID_WIDTH-1:0]	Output		–	–	Write channel transaction ID.
m_axi_wready[M-1:0]	Input				Write channel ready.

Table 9. Write Response Channel (Master)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
m_axi_bready[M-1:0]	Output				Write response channel ready.
m_axi_bresp[M*2-1:0]	Output				Write response channel response.
m_axi_bvalid[M-1:0]	Output				Write response channel valid.
m_axi_bid[M*ID_WIDTH-1:0]	Output			–	Write response channel transaction ID. Tie to `0` when using AXI Lite.
m_axi_buser[M*USER_WIDTH-1:0]	Input	–		–	Write response channel user-defined ID.

Table 10. Read Address Channel (Master)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
m_axi_arvalid[M-1:0]	Output				Read address channel valid.
m_axi_araddr[M*ADDR_WIDTH-1:0]	Output				Read address channel address.
m_axi_arprot[M*3-1:0]	Output				Read address channel protect.
m_axi_arid[M*ID_WIDTH-1:0]	Output			–	Read address channel transaction ID.
m_axi_arburst[M*2-1:0]	Output			–	Read address channel burst type.
m_axi_arlen[M*8-1:0]	Output			–	Read address channel burst length.
m_axi_arsize[M*3-1:0]	Output			–	Read address channel transfer size.
m_axi_arcache[M*4-1:0]	Output	–		–	Read address channel cache encoding.
m_axi_arqos[M*4-1:0]	Output	–		–	Read address channel QoS.
m_axi_aruser[M*USER_WIDTH-1:0]	Output	–		–	Read address channel user-defined signals.
m_axi_arlock[M*2-1:0]	Output		–	–	Read address channel locked transaction.
m_axi_arready[M-1:0]	Input				Read address channel ready.

Table 11. Read Data Channel (Master)
Port	Direction	AXI3	AXI4	AXI4-Lite	Description
m_axi_rready[M-1:0]	Output				Read data channel ready.
m_axi_rid[M*ID_WIDTH-1:0]	Output			–	Read data channel transaction ID. Tie to `0` when using AXI Lite.
m_axi_rdata[M*DATA_WIDTH-1:0]	Output				Read data channel data.
m_axi_rresp[M*2-1:0]	Output				Read data channel response.
m_axi_rvalid[M-1:0]	Output				Read data channel valid.
m_axi_rlast[M-1:0]	Output			–	Read data channel last data beat. Tie to `1` when using AXI Lite.
m_axi_ruser[M*USER_WIDTH-1:0]	Input	–		–	Read data user-defined channel.