Functional Description

The AXI Data FIFO consist of a FIFO for each of the channel in the AXI protocol (except for the write response channel). There are two modes of data FIFO that can be configured for each of the write and read paths:

Block RAM based FIFO—Supported for 32 or 512-deep FIFO (data channel only)
Block RAM based Packet FIFO—Supported for 512-deep FIFO only (Write/Read Address FIFO)

Figure 1. AXI Data FIFO Core Block Diagram

The packet FIFO mode (Write/Read Address FIFO) is utilized to prevent full/empty stalls during bursts. Alongside the 512-deep FIFO on the data channel, packet mode also incorporates a 32-deep FIFO on the corresponding address channel. When write packet mode is enabled, the write transaction on the AW channel experiences a delay until the complete write data burst (concluded with WLAST) has been received on the SI. This delay ensures that stalling caused by a slow write data source is avoided. Similarly, when read packet mode is enabled, the read transaction on the AR channel is delayed until the FIFO has sufficient vacancy to store the entire burst according to ARLEN. The term vacancy refers to the remaining free space in the read channel FIFO that has not been committed by previously issued AR commands. This approach prevents stalling due to a slow read destination.