Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Packet Mode | Logic Elements1 | Memory Block | DSP Block | fMAX (MHz) | Efinity Version |
|---|---|---|---|---|---|---|
| T20 BGA256 | Yes | 330/19728 (2%) | 16 / 204 (8%) | 0/36 (0%) | 300 | 2023.1 |
| No | 136/19728 (<1%) | 8 / 204 (4%) | 0/36 (0%) | 100 | 2023.1 | |
| Ti60 F225 | Yes | 330/60800 (<1%) | 37/256 (14%) | 0/160 (0%) | 400 | 2023.1 |
| No | 330/60800 (<1%) | 4/256 (2%) | 0/160 (0%) | 125 | 2023.1 |
1 Logic, Adders, Flipflops, etc.