Packet Mode Operations

You can enable the packet mode by enabling the Write Address FIFO or Read Address FIFO parameter in the IP Manager. When enabled, you will observe a 2-clock cycle delay between the slave and the master address channel. The write and read address channel acts like a pass through when the packet mode is disabled

The following figures describe timing sequences on the AXI write and read address channels with the address FIFO enabled and disabled.

Figure 1. Write Address FIFO Enabled
Figure 2. Write Address FIFO Disabled
Figure 3. Read Address FIFO Enabled
Figure 4. Read Address FIFO Disabled