Ports

Table 1. Global Interface

Port	Direction	Description
aclk	Input	Core clock.
aresetn	Input	Active-low asynchronous reset.

Table 2. Slave Interface Write Address Channel

Port	Direction	Description
s_axi_awvalid	Input	Write address channel valid.
s_axi_awaddr [ADDR_WIDTH-1:0]	Input	Write address channel address.
s_axi_awprot [2:0]	Input	Write address channel protect.
s_axi_awid [ID_WIDTH-1:0]	Input	Write address channel transaction ID.
s_axi_awburst [1:0]	Input	Write address channel burst type.
s_axi_awlen [7:0]	Input	Write address channel burst length.
s_axi_awsize [2:0]	Input	Write address channel transfer size.
s_axi_awcache [3:0]	Input	Write address channel cache encoding.
s_axi_awqos [3:0]	Input	Write address channel QoS.
s_axi_awuser [AWUSER_WIDTH-1:0]	Input	Write address channel user-defined signals.
s_axi_awlock [1:0]	Input	Write address channel locked transaction.
s_axi_awregion [3:0]	Input	Write address channel region identifier. Not applicable to AXI3.
s_axi_awready	Output	Write address channel ready.

Table 3. Slave Interface Write Data Channel

Port	Direction	Description
s_axi_wvalid	Input	Write data channel valid.
s_axi_wdata [DATA_WDITH-1:0]	Input	Write data channel data.
s_axi_wstrb [DATA_WIDTH/8-1:0]	Input	Write data channel strobe. Single bit represents data byte.
s_axi_wlast	Input	Write data channel data beat.
s_axi_wuser [WUSER_WIDTH-1:0]	Input	Write data channel user-defined signals.
s_axi_wid [ID_WIDTH-1:0]	Input	Write data channel transaction ID.
s_axi_wready	Output	Write data channel ready.

Table 4. Slave Interface Write Response Channel

Port	Direction	Description
s_axi_bready	Input	Write response channel ready.
s_axi_bresp [1:0]	Output	Write response channel response.
s_axi_bvalid	Output	Write response channel valid.
s_axi_bid [ID_WIDTH-1:0]	Output	Write response channel transaction ID.
s_axi_buser [BUSER_WIDTH-1:0]	Output	Write response channel user-defined signals.

Table 5. Slave Interface Read Address Channel

Port	Direction	Description
s_axi_arvalid	Input	Read address channel valid.
s_axi_araddr [ADDR_WIDTH-1:0]	Input	Read address channel address.
s_axi_arprot [2:0]	Input	Read address channel protect.
s_axi_arid [ID_WIDTH-1:0]	Input	Read address channel transaction ID.
s_axi_arburst [1:0]	Input	Read address channel burst type.
s_axi_arlen [7:0]	Input	Read address channel burst length.
s_axi_arsize [2:0]	Input	Read address channel size.
s_axi_arcache [3:0]	Input	Read address channel cache encoding.
s_axi_arqos[3:0]	Input	Read address channel QoS.
s_axi_aruser [ARUSER_WIDTH-1:0]	Input	Read address channel user-defined signals.
s_axi_arlock [1:0]	Input	Read address channel locked transaction.
s_axi_arregion [3:0]	Input	Read address channel region identifier. Not applicable to AXI3.
s_axi_arready	Output	Read address channel ready.

Table 6. Slave Interface Read Data Channel

Port	Direction	Description
s_axi_rready	Input	Read data channel ready.
s_axi_rid [ID_WIDTH-1:0]	Output	Read data channel transaction ID.
s_axi_rdata [DATA_WDITH-1:0]	Output	Read data channel data.
s_axi_rresp [1:0]	Output	Read data channel read response.
s_axi_rvalid	Output	Read data channel valid.
s_axi_rlast	Output	Read data channel last data beat.
s_axi_ruser [RUSER_WIDTH-1:0]	Output	Read data channel user-defined channel.

Table 7. Master Interface Write Address Channel

Port	Direction	Description
m_axi_awvalid	Output	Write address channel valid.
m_axi_awaddr [ADDR_WIDTH-1:0]	Output	Write address channel address.
m_axi_awprot [2:0]	Output	Write address channel protect.
m_axi_awid [ID_WIDTH-1:0]	Output	Write address channel transaction ID.
m_axi_awburst [1:0]	Output	Write address channel burst type.
m_axi_awlen [7:0]	Output	Write address channel transaction length.
m_axi_awsize [2:0]	Output	Write address channel transfer size.
m_axi_awcache [3:0]	Output	Write address channel cache encoding.
m_axi_awqos [3:0]	Output	Write address channel QoS.
m_axi_awuser [AWUSER_WIDTH-1:0]	Output	Write address channel user-defined signal.
m_axi_awlock [1:0]	Output	Write address channel locked.
m_axi_awregion [3:0]	Output	Write address channel region identifier. Not applicable to AXI3.
m_axi_awready	Input	Write address channel ready.

Table 8. Master Interface Write Data Channel

Port	Direction	Description
m_axi_wvalid	Output	Write data channel valid.
m_axi_wdata [DATA_WDITH-1:0]	Output	Write data channel data.
m_axi_wstrb [DATA_WDITH/8-1:0]	Output	Write data channel strobe. Single bit represents data byte.
m_axi_wlast	Output	Write data channel last data beat.
m_axi_wuser [WUSER_WIDTH-1:0]	Output	Write data channel user-defined signals.
m_axi_wid [ID_WIDTH-1:0]	Output	Write data channel transaction ID.
m_axi_wready	Input	Write data channel ready.

Table 9. Master Interface Write Response Channel

Port	Direction	Description
m_axi_bready	Output	Write response channel ready.
m_axi_bresp [1:0]	Input	Write response channel response.
m_axi_bvalid	Input	Write response channel valid.
m_axi_bid [ID_WIDTH-1:0]	Input	Write response channel transaction ID.
m_axi_buser [BUSER_WIDTH-1:0]	Input	Write response channel user-defined signals.

Table 10. Master Interface Read Address Channel

Port	Direction	Description
m_axi_arvalid	Output	Read address channel valid.
m_axi_araddr [ADDR_WIDTH-1:0]	Output	Read address channel address.
m_axi_arprot [2:0]	Output	Read address channel protect.
m_axi_arid [ID_WIDTH-1:0]	Output	Read address channel transaction ID.
m_axi_arburst [1:0]	Output	Read address channel burst type.
m_axi_arlen [7:0]	Output	Read address channel burst length.
m_axi_arsize [2:0]	Output	Read address channel transfer size.
m_axi_arcache [3:0]	Output	Read address channel cache encoding.
m_axi_arqos [3:0]	Output	Read address channel QoS.
m_axi_aruser	Output	Read address channel user define signals.
m_axi_arlock [1:0]	Output	Read address channel locked.
m_axi_arregion [3:0]	Output	Read address channel region identifier.
m_axi_arready	Input	Read address channel ready.

Table 11. Master Interface Read Data Channel

Port	Direction	Description
m_axi_rready	Output	Read data channel ready.
m_axi_rid [ID_WIDTH-1:0]	Input	Read data channel transaction ID.
m_axi_rdata [DATA_WDITH-1:0]	Input	Read data channel data.
m_axi_rresp [1:0]	Input	Read data channel response.
m_axi_rvalid	Input	Read data channel valid.
m_axi_rlast	Input	Read data channel last data beat.
m_axi_ruser [RUSER_WIDTH-1:0]	Input	Read data channel user define signals.