ASMI SPI Flash Controller Testbench

You can choose to generate the testbench when generating the core in the IP Manager Configuration window. To generate testbench, the Testbench Deliverables Option signals must be enabled.

Note: You must include all .v files generated in the /Testbench directory in your simulation.
Important: tested the testbench generated with the default parameter options only.

provides a simulation script for you to run the testbench quickly using the Modelsim software. To run the Modelsim testbench script, run vsim -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

The testbench performs the erase, write, and read commands to the flash memory. The testbench uses these files:
  • MEM.TXT—Model for the memory data in the flash device
  • SREG.TXT—Model for data for flash device status register
  • W25Q256JV.v—Flash memory model
Note: The testbench does not support quad operations.

Before running the simulation, uncomment line 17 in the dbg_defines.v file to shorten the simulation run time.

After running the write simulation, the test prints the following message:
00110011