ASMI SPI Flash Controller Core Ports

Table 1. User Interface Ports
Port Direction Description
clk_in Input System clock.
rst_in Input Active high synchronous reset. During the reset, the controller sends a software reset to the flash device.
fast_read Input Active-high port that executes fast read operation. When asserted, the core performs a fast read operation from the flash address specified by address[n:0].
fast_read_dual Input Active-high port that executes a fast read dual operation.
sector_erase Input Active-high port that executes a sector erase operation. When asserted, the core performs a sector erase operation on the flash address specified by address[n:0].
page_write Input Active-high port that executes a write operation. When asserted, the core writes the data from the page-write buffer to the flash memory address specified by address[n:0].
During a page-write operation, use shift_bytes to shift in the data bytes before asserting page_write.
address[ADDR_WIDTH-1:0] Input Flash address to read from, write to, or erase.
datain[7:0] Input Parallel 8-bits/1-byte data for page write operations.
rden Input Active-high read. While asserted, the core can perform read, fast read, and fast read dual operations.
wren Input Active-high write. While asserted, the core can perform write and erase operations. Use with page_write and sector_erase.
shift_bytes Input Active-high port that shifts data bytes during a write operation. Use with page_write during page write operations. While shift_bytes is asserted, the core store data on datain[7:0] on the rising edge of clk_in. Shift the required bytes into the flash device until the core finishes storing the data internally.
busy Output Indicates that the core is performing a valid operation. Goes high when the core is executing a valid operation; goes low when the operation completes.
dataout[7:0] Output Contains the data byte read from flash memory during read operations. This port holds the value of the last data byte read until new a read operation occurs.
data_valid Output Indicates that dataout[7:0] contains a valid data byte read from flash memory.
quad_enable Input Enables quad mode for the flash. Enabling quad mode disables the WPN and HOLD ports of the flash.
quad_fast_read Input Active-high port that executes a fast read quad operation.
quad_page_write Input Active-high port that executes a page write quad operation. When asserted, the core writes the data from the page write buffer to the flash memory address specified by address[23:0]. During a page write operation, use shift_bytes to shift in the data bytes before asserting quad_page_write.
read_deviceID Input Active-high port that releases the device from power-down state or read Device ID.
block_erase_64k Input Active-high port that executes a block erase operation. When asserted, the core performs a block erase operation on the flash address specified by address[n:0].
fourbyte_addr_enable Input Enables 4-byte addressing mode.
Table 2. SPI Ports
Port Direction Description
miso Input Serial data. Bit 0 in fast read dual and quad mode operations.
miso_1 Input Serial data. Bit 1 in fast read dual and quad mode operations.
miso_2 Input Serial data. Bit 2 in fast read quad mode operations.
miso_3 Input Serial data. Bit 3 in fast read quad mode operations.
sclk Output SPI clock.
nss Output SPI active low chip select.
mosi Output Serial data out. Bit 0 for page write, quad page write and erase operations.
mosi_1 Output Serial data out. Bit 1 quad mode operations.
mosi_2 Output Serial data out. Bit 2 quad mode operations.
mosi_3 Output Serial data out. Bit 3 quad mode operations.
mosi_oe Output Serial data out enable.