ASMI SPI Flash Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example designs target the Trion® T20 BGA256 Development Board, Trion T120 BGA324 Development Board, Titanium Ti60 F225 Development Board, and Titanium Ti180 M484 Development Board. The design implements a ASMI SPI flash controller in the FPGA, which allows you to use the ASMI SPI flash controller to access the flash memory via sector erase, write, and read commands. The maximum supported frequency is 50 MHz.

Figure 1. ASMI SPI Flash Controller Example Design
Table 1. Example Design Support
Development Board Example Design
T20 BGA256 Dual read and write operations using 3-byte addressing mode.
Ti60 F225
T120 BGA324 Dual read and write, quad read and write operations using 3-byte addressing mode.
Ti180 M484 Dual read and write operations using 3-byte and 4-byte addressing modes.
Table 2. Titanium Example Design Implementation
FPGA Logic Elements (Logic, adders, Flipflops, etc.) Memory Blocks DSP Blocks fMAX (MHz) Efinity® Version1
Ti60 F225 C4 2,004/60,800 (2.69%) 1/256 (0.39%) 0 231 2022.2
Ti180 M484 C4 1,884/172,800 (1.09%) 1/1,280 (0.08%) 0 224 2022.2
Table 3. Trion® Example Design Implementation
FPGA LUTs Registers Memory Blocks Multipliers fMAX (MHz) Efinity Version1
T20 BGA256 C4 1,576 466 2 0 127 2022.2
T120 BGA324 C4 1,629 617 2 0 119 2022.2

T20 BGA256 and Ti60 F225 Development Board Example Design

After the FPGA powers up, the ASMI SPI flash controller performs this sequence:
  1. Soft reset.
  2. Set address to 0x350000.
  3. Sector erase at address 0x350000.
  4. Write 8-bit data (0x5A) to address 0x350000.
  5. Fast read from address 0x350000.
  6. Set address to 0x000004.
  7. Sector erase at address 0x000004.
  8. Write 8-bit data (0x33) to address 0x000004.
  9. Fast read dual from address 0x000004
  10. Set address to 0x050000.
  11. Release the device from power-down state.
  12. Set address to 0x0000ff.
  13. Block erase at address 0x0000ff.
  14. Write 8-bit data (0x50) to address 0x0000ff.
  15. Fast read dual from address 0x0000ff.
  16. Set address to 0x000024.
  17. Block erase at address 0x000024.
  18. Write 8-bit data (0x23) to address 0x000024.
  19. Fast read from address 0x000024.
  20. When done, the LEDs display:
    • T20 BGA256 Development Board—LEDs D4 and D3 turned on
    • Ti60 F225 Development Board—LED D16 turned on blue and green, and LED D17 turned on red
Figure 2. Titanium Ti60 F225 Development Board LED Outputs

Ti180 M484 Development Board Example Design

After the FPGA powers up, the ASMI SPI flash controller performs this sequence:
  1. Soft reset.
  2. Set address to 0x350000.
  3. Sector erase at address 0x350000 (4-byte addressing).
  4. Write 8-bit data (0x5A) to address 0x350000 (4-byte addressing).
  5. Fast read from address 0x350000 (4-byte addressing).
  6. Set address to 0x000004.
  7. Sector erase at address 0x000004 (3-byte addressing).
  8. Write 8-bit data (0x33) to address 0x000004 (3-byte addressing).
  9. Fast read dual from address 0x000004 (3-byte addressing).
  10. Set address to 0x050000.
  11. Release the device from power down state.
  12. Set address to 0x0000ff.
  13. Block erase at address 0x0000ff (4-byte addressing).
  14. Write 8-bit data (0x50) to address 0x0000ff (4-byte addressing).
  15. Fast read dual from address 0x0000ff (4-byte addressing).
  16. Set address to 0x000024.
  17. Block erase at address 0x000024 (3-byte addressing).
  18. Write 8-bit data (0x23) to address 0x000024 (3-byte addressing).
  19. Fast read from address 0x000024 (3-byte addressing).
  20. When done, the LEDs D2, D3, and D7 turned on.

T120 BGA324 Development Board Example Design

Set the QUAD_EN parameter to 1 in the flash_test_ctl.v file to enable quad operations. After the FPGA powers up, the ASMI SPI flash controller performs this sequence:
  1. Soft reset.
  2. Set address to 0x350000.
  3. Sector erase at address 0x350000.
  4. Write 8-bit data (0x5A) to address 0x350000.
  5. Fast read from address 0x350000.
  6. Set address to 0x000004.
  7. Sector erase at address 0x000004.
  8. Write 8-bit data (0x33) to address 0x000004.
  9. Fast read dual from address 0x000004.
  10. Set address to 0x050000.
  11. Release the device from power down state.
  12. Set address to 0x0000ff.
  13. Block erase at address 0x0000ff.
  14. Write 8-bit data (0x50) to address 0x0000ff.
  15. Fast read dual from address 0x0000ff.
  16. Set address to 0x000024.
  17. Block erase at address 0x000024.
  18. Write 8-bit data (0x23) to address 0x000024.
  19. Fast read from address 0x000024.
  20. Sector erase.
  21. Quad page writes 8-bit data (0XC3) to address 0x000010.
  22. Read from address 0x000010.
  23. Quad read from address 0x000010.
  24. When done, the LEDs D7 and D8 turned on.
1 Using Verilog HDL.