Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Logic Elements (Logic, adders, Flipflops, etc.) | Memory Blocks | DSP Blocks | fMAX (MHz) | Efinity® Version1 |
|---|---|---|---|---|---|
| Ti60 F225 C4 | 1,626/60,800 (2.67%) | 1/256 (0.39%) | 0 | 443 | 2022.2 |
| Ti180 M484 C4 | 1,626/172,800 (0.94%) | 1/1,280 (0.08%) | 0 | 414 | 2022 |
| FPGA | Logic Utilization (LUTs) | Registers | Memory Blocks | Multipliers | fMAX (MHz) | Efinity® Version1 |
|---|---|---|---|---|---|---|
| T20 BGA256 C4 | 1,597 | 305 | 2 | 0 | 131 | 2022.2 |
| T120 BGA324 C4 | 1,597 | 305 | 2 | 0 | 129 | 2022.2 |
1 Using Verilog HDL.