Functional Description

The SD Host Controller core consists of the following modules:
  • Clock Management—Manages and generates clock source to SD receiver.
  • SD Command Control—Transits command out from SD host controller and listening response from SD receiver
  • SD Data Control—Transits data out from SD host controller and receive data coming back from SD receiver
  • Buffer Control—Manages incoming data traffic and outgoing data traffic.
  • DMA Engine—Manages ADMA data transfer protocol.
  • Register—Stores control setting for host controller and status/response from SD receiver.
Figure 1. SD Host Controller PLL Calibration Block Diagram