Register Definition

Table 1. Register Description
Address Offset Name R/W
0x000 Version RO
0x004 Base Register 0 R/W
0x008 Base Status Register 0 RO
0x100 Argument 2[31:0] R/W
0x104 Block Size Register
Block Count Register
 R/W
0x108 Argument 1[31:0] R/W
0x10C Transfer Mode Register
Command Register
 R/W
0x110 Command_Response [31:0] RO
0x114 Command_Response [63:32] RO
0x118 Command_Response [95:64] RO
0x11c Command_Response [127:96] RO
0x120 Buffer Data Port Register R/W
0x124 Present State Register R/W
0x128 Host Control 1 Register
Power Control Register
Block Gap Control Register
Wakeup Control Register
 R/W
0x12c Clock Control Register
Timeout Control Register
Software Reset Register
 R/W
0x130 Normal Interrupt Status Register
Error Interrupt Status Register
 R/W
0x134 Normal Interrupt Status Enable Register
Error Interrupt Status Enable Register
 R/W
0x138 Normal Interrupt Status Enable Register
Error Interrupt Status Enable Register
 R/W
0x140 Host capabilities RO
0x158 ADMA System Address Register (Lower Word) R/W
0x15C ADMA System Address Register (Upper Word) R/W
Table 2. Base Register 0 (0x004)
Bits I/O Description R/W
31-17 - Reserved. -
16 Input Clock Enable. R/W
15-0 Input Clock divider factor. R/W
Table 3. Base Status Register 0 (0x008)
Bits I/O Description R/W
31-3 - Reserved. -
2 Output SD Card detection:
0: Detected
1: Not Detected
 RO
1 Output Data line is busy:
0: Not Busy
1: Busy
 RO
0 Output Command line is busy:
0: Not Busy
1: Busy
 RO
Table 4. Argument 2 Register (0x100)
Bits I/O Description R/W
31-0 Input Argument 2.
Contains the physical system memory address used for ADMA transfers.
 R/W
Table 5. Block Size Register (0x104)
Bits I/O Description R/W
15 - Reserved. R/W
14-12 Input Host ADMA Buffer Boundary.
Specifies the size of contiguous buffer in the system memory. The ADMA transfer waits at every boundary specified by these fields and the host controller generates the ADMA Interrupt to request the host driver to update the ADMA System Address register.
000b: 4 KB
001b: 8 KB
010b: 16 KB
011b: 32 KB
100b: 64 KB
101b: 128 KB
110b: 256 KB
111b: 512 KB
 R/W
11-0 Input Transfer Block Size.
Specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size can be set. For memory, set to 512 bytes.
0000h: No data transfer
0001h: 1 byte
0002h: 2 bytes
...
0200h: 512 bytes
...
0800h: 2048 bytes
 R/W
Table 6. Block Count Register (0x104)
Bits I/O Description R/W
31-16 Input Blocks Count for Current Transfer.
Enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The host driver sets this register to a value between 1 and the maximum block count.
0000h: Stop Count
0001h: 1 block
0002h: 2 blocks
...
FFFFh: 65535 blocks
 R/W
Table 7. Argument 1 Register (0x108)
Bits I/O Description R/W
31-0 Input Command Argument 1.
The SD command argument is specified as bit 39-8 of Command-Format in the Physical Layer Specification.
 R/W
Table 8. Transfer Mode Register (0x10C)
Bits I/O Description R/W
16-5 Input Reserved R/W
5 Input Multi/Single Block Select.
Set when issuing multiple-block transfer commands using DATA line.
0: Single Block
1: Multiple Block
 R/W
4 Input Data Transfer Direction Select.
Defines the direction of DAT line data transfers.
0: Write (Host to Card)
1: Read (Card to Host)
 R/W
3-2 Input Auto CMD Enable.
Sets the auto command functions.
00b: Auto Command Disabled
01b: Auto CMD12 Enable
10b: Auto CMD23 Enable
11b: Reserved
 R/W
1 Input Block Count Enable
Enables the Block Count register, which is only relevant for multiple block transfers. If ADMA data transfer is more than 65535 blocks, this bit shall be set to 0. In this case, data transfer length is designated by the descriptor table.
0: Disable
1: Enable
 R/W
0 Input DMA Enable.
Enables the DMA functionality.
0: No data transfer or Non DMA data transfer
1: DMA Data transfer
Table 9. Command Register (0x10C)
Bits I/O Description R/W
31-30 - Reserved. -
29-24 Input Command Index.
Set to the command number (CMD0-63, ACMD0-63).
 R/W
23-22 Input Command Type.
There are three types of special commands: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands.
00b: Other commands
01b: CMD52 for writing "Bus Suspend" in CCCR
10b: CMD52 for writing "Function Select" in CCCR
11b: CMD12, CMD52 for writing "I/O Abort" in CCCR
R/W
21 Input Data Present Select.
Set to 1 to indicate that data is present.
 R/W
20 Input Command Index Check Enable.
Set to 1 for the host controller to check the index field in the response to see if it has the same value as the command index.
 R/W
19 Input Command CRC Check Enable.
Set to 1 for the host controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error.
 R/W
18 - Reserved. -
17-16 Input Response Type Select.
00b: No Response
01b: Response Length 136
10b: Response Length 48
11b: Response Length 48 check Busy after response
 R/W
Table 10. Command Response Register (0x110 – 0x11C)
Offset I/O Description R/W
0x110 Output Command Response 0 – 31. RO
0x114 Output Command Response 63 – 32. RO
0x118 Output Command Response 95 – 64. RO
0x11C Output Command Response 127 – 96. RO
Table 11. Buffer Data Port Register (0x120)
Bits I/O Description R/W
31-0 Input 32-bit data port register to access internal buffer. R/W
Table 12. Present State Register (0x124)
Bits I/O Description R/W
15-12 - Reserved. -
11 Output Buffer Read Enable.
Used for non-DMA read transfers.
0: Read Disable
1: Read Enable
 RO
10 Output Buffer Write Enable.
Used for non-DMA write transfers.
0: Write Disable
1: Write Enable
 RO
9 Output Read Transfer Active.
Indicates completion of a read transfer.
0: No valid data
1: Transferring data
RO
8 Output Write Transfer Active.
Indicates a write transfer is active.
0: No valid data
1: Transferring data
RO
7-4 - Reserved. -
3 Input Re-Tuning Request. Not supported. R/W
2 Output DAT Line Active.
Indicates whether one of the DAT line on SD Bus is in use.
0: DAT Line Inactive
1: DAT Line Active
 RO
1 Output Command Inhibit (DAT).
Indicates if either the DAT Line Active or the Read Transfer Active is set to 1.
0: Can issue command which uses the DAT line
1: Cannot issue command which uses the DAT line
 RO
0 Output Command Inhibit (CMD).
Indicates that the CMD line is not in use and the host controller can issue a SD Command using the CMD line.
0: Can issue command using only CMD line
1: Cannot issue command
 RO

Table 13. Host Control 1 Register (0x128)
Bits I/O Description R/W
7-2 - Reserved. -
1 Input Data Transfer Width.
Selects the data width of the host controller.
 R/W
0 Input LED Control.
Used to caution the user not to remove the card while the SD card is being accessed.
0: LED off
1: LED on
 R/W
Table 14. Power Control Register (0x128)
Bits I/O Description R/W
15-8 - Reserved. -
Table 15. Block Gap Control Register (0x128)
Bits I/O Description R/W
23-20 - Reserved. -
19 Input Interrupt At Block Gap.
Enables interrupt detection at the block gap for a multiple block transfer.
0: Disable
1: Enable
 R/W
18 Input Read Wait Control.
If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using the DAT[2] line.
0: Enable Read Wait Control
1: Disable Read Wait Control
 R/W
17 Input Continue Request.
Restart a transaction, which was stopped by the Stop At Block Gap Request.
0: Not affect
1: Restart
 R/W
16 Input Stop At Block Gap Request.
Stop executing read and write transaction at the next block gap for non-DMA, SDMA and ADMA transfers
0: Transfer
1: Stop
 R/W
Table 16. Wake up Control Register (0x128)
Bits I/O Description R/W
7-0 - Reserved. -

Table 17. Clock Control, Timeout and Software Register (0x12C)
Bits I/O Description R/W
31-0 - Reserved. -
Table 18. Normal Interrupt Status Register (0x130)
Bits I/O Description R/W
15-9 - Reserved. -
8 Output Card Interrupt.
0: No interrupt
1: Interrupt Detected
 RO
7 Output Card Removal.
0: No interrupt
1: Interrupt Detected
 RO
6 Output Card Insertion.
0: No interrupt
1: Interrupt Detected
 RO
5 Output Buffer Read Ready.
0: No interrupt
1: Interrupt Detected
 RO
4 Output Buffer Write Ready.
0: No interrupt
1: Interrupt Detected
 RO
3 - Reserved -
2 Output Block Gap Event.
0: No interrupt
1: Interrupt Detected
 RO
1 Output Transfer Complete.
0: No interrupt
1: Interrupt Detected
 RO
0 Output Command Complete.
0: No interrupt
1: Interrupt Detected
 RO

Table 19. Error Interrupt Status Register (0x130)
Bits I/O Description R/W
31-22 - Reserved. -
21 Output Data CRC Error.
0: No interrupt
1: Interrupt Detected
 RO
20 - Reserved. -
19 Output Command Index Error.
0: No interrupt
1: Interrupt Detected
 RO
18 Output Command End Bit Error.
0: No interrupt
1: Interrupt Detected
 RO
17 Output Command CRC Error.
0: No interrupt
1: Interrupt Detected
 RO
16 Output Command Timeout Error.
0: No interrupt
1: Interrupt Detected
 RO

Table 20. Normal Interrupt Status Enable Register (0x134)
Bits I/O Description R/W
15-9 - Reserved. -
8 Input Card Interrupt.
0: No interrupt
1: Interrupt Detected
 R/W
7 Input Card Removal.
0: No interrupt
1: Interrupt Detected
 R/W
6 Input Card Insertion.
0: No interrupt
1: Interrupt Detected
 R/W
5 Input Buffer Read Ready.
0: No interrupt
1: Interrupt Detected
 R/W
4 Input Buffer Write Ready.
0: No interrupt
1: Interrupt Detected
 R/W
3 - Reserved -
2 Input Block Gap Event.
0: No interrupt
1: Interrupt Detected
 R/W
1 Input Transfer Complete.
0: No interrupt
1: Interrupt Detected
 R/W
0 Input Command Complete.
0: No interrupt
1: Interrupt Detected
 R/W

Table 21. Error Interrupt Status Enable Register (0x134)
Bits I/O Description R/W
31-22 - Reserved. -
21 Input Data CRC Error.
0: No interrupt
1: Enable interrupt
 R/W
20 - Reserved. -
19 Input Command Index Error.
0: No interrupt
1: Enable interrupt
 R/W
18 Input Command End Bit Error.
0: No interrupt
1: Enable interrupt
 R/W
17 Input Command CRC Error.
0: No interrupt
1: Enable interrupt
 R/W
16 Input Command Timeout Error.
0: No interrupt
1: Enable interrupt
 R/W

Table 22. Normal Interrupt Signal Enable Register (0x138)
Bits I/O Description R/W
15-9 - Reserved. -
8 Input Card Interrupt.
0: Masked
1: Enabled
 R/W
7 Input Card Removal.
0: Masked
1: Enabled
 R/W
6 Input Card Insertion.
0: Masked
1: Enabled
 R/W
5 Input Buffer Read Ready.
0: Masked
1: Enabled
 R/W
4 Input Buffer Write Ready.
0: Masked
1: Enabled
 R/W
3 - Reserved. -
2 Input Block Gap Event.
0: Masked
1: Enabled
 R/W
1 Input Transfer Complete.
0: Masked
1: Enabled
 R/W
0 Input Command Complete.
0: Masked
1: Enabled
 R/W

Table 23. Error Interrupt Signal Enable Register (0x138)
Bits I/O Description R/W
31-22 - Reserved. -
21 Input Data CRC Error.
0: Masked
1: Enabled
 R/W
20 - Reserved. -
19 Input Command Index Error.
0: Masked
1: Enabled
 R/W
18 Input Command End Bit Error.
0: Masked
1: Enabled
 R/W
17 Input Command CRC Error.
0: Masked
1: Enabled
 R/W
16 Input Command Timeout Error.
0: Masked
1: Enabled
 R/W
Table 24. Host Capabilities Register (0x140)
Bits I/O Description R/W
32-63 - Reserved. RO
31-30 Output Slot type.
This field indicates the usage of a slot by a specific host system.
 RO
28-25 - Reserved. -
24 Output 3.3 VDD1 support.
This field indicates that 3.3V VDD1 is supported.
RO
23-22 - Reserved. RO
21 Output High speed support.
This field indicates the host controller can supply SD Clock frequency of 25MHz to 50MHz.
 RO
20 - Reserved. -
19 Output ADMA2 support.
This field indicates that ADMA2 is supported.
 RO
18 - Reserved. -
17-16 Output Max block length.
This field indicates the maximum block size that the host driver can read and write to the buffer in the host controller.
RO
15-8 Output Base clock frequency for SD Clock.
This field indicates the base (maximum) clock frequency for the SD clock.
RO
7-0 - Reserved. -
Table 25. ADMA System Address Register (0x158)
Bits I/O Description R/W
31-0 - ADMA System Address (Lower Word).
Holds byte address of executing command of the descriptor table.
 R/W
Table 26. ADMA System Address Register (0x15C)
Bits I/O Description R/W
31-0 - ADMA System Address (Upper Word).
Holds byte address of executing command of the descriptor table.
 R/W