Ports

Table 1. SD Host Controller Clock and Reset Interface
Name Direction Description
sd_clk Input SD base clock.
sd_rst Input SD base reset.
Table 2. SD Card Interface
Name Direction Description
sd_clk_o Output SD card clock.
sd_cmd_i Input SD card command input.
sd_cmd_o Output SD card command output
sd_cmd_oe Output SD card command output enable.
sd_dat_i [3:0] Input SD card data input.
sd_dat_o [3:0] Output SD card data output.
sd_dat_oe Output SD card data Output output enable.
Table 3. SD Card Auxiliary Signal Interface
Name Direction Description
sd_int Output SD interrupt.
sd_wp Input SD write protect switch.
sd_cd_n Input SD card not present.
Table 4. AXI4-Lite Slave Register Interface
Name Direction Description
s_axi_aclk Input AXI4-Lite interface clock.
s_axi_awaddr [9:0] Input AXI4-Lite write address bus.
s_axi_awvalid Input AXI4-Lite write address valid strobe.
s_axi_awready Output AXI4-Lite write address ready signal.
s_axi_wdata [31:0] Input AXI4-Lite write data.
s_axi_wstrb [3:0] Input AXI4-Lite write strobe.
s_axi_wvalid Input AXI4-Lite write data valid strobe.
s_axi_wready Output AXI4-Lite write ready signal.
s_axi_bresp [1:0] Output AXI4-Lite write response.
s_axi_bvalid Output AXI4-Lite write response valid strobe.
s_axi_bready Input AXI4-Lite write response ready signal.
s_axi_araddr [9:0] Input AXI4-Lite read address bus.
s_axi_arvalid Input AXI4-Lite read address valid strobe.
s_axi_arready Output AXI4-Lite read address ready signal.
s_axi_rdata [31:0] Output AXI4-Lite read data.
s_axi_rresp [1:0] Output AXI4-Lite read response.
s_axi_rvalid Output AXI4-Lite read data valid strobe.
s_axi_rready Input AXI4-Lite read data ready signal.
Table 5. AXI4 Master Memory InterfaceWhere n= 32, 64, 128, 256, 512
Name Direction Description
m_axi_clk Input AXI4 interface clock.
m_axi_awaddr [31:0] Output AXI4 write address.
m_axi_awlen [7:0] Output AXI4 write burst length.
m_axi_awsize [2:0] Output AXI4 write burst size.
m_axi_awburst [1:0] Output AXI4 write burst type.
m_axi_awlock [1:0] Output AXI4 write lock type.
m_axi_awcache [3:0] Output AXI4 write cache type.
m_axi_awprot [2:0] Output AXI4 write protection type.
m_axi_awvalid Output AXI4 write address valid.
m_axi_awready Input AXI4 write address ready.
m_axi_wdata [n-1:0] Output AXI4 write data.
m_axi_wstrb [n/8-1:0] Output AXI4 write strobes.
m_axi_wlast Output AXI4 write last.
m_axi_wvalid Output AXI4 write valid.
m_axi_wready Input AXI4 write ready.
m_axi_bresp [1:0] Input AXI4 write response.
m_axi_bvalid Input AXI4 write response valid.
m_axi_bready Output AXI4 write response ready.
m_axi_araddr [31:0] Output AXI4 read address.
m_axi_arlen [7:0] Output AXI4 read burst length.
m_axi_arsize [2:0] Output AXI4 read burst size.
m_axi_arburst [1:0] Output AXI4 read burst type.
m_axi_arlock [1:0] Output AXI4 read lock type.
m_axi_arcache [3:0] Output AXI4 read cache type.
m_axi_arprot [2:0] Output AXI4 read protection type.
m_axi_arvalid Output AXI4 read address valid.
m_axi_arready Input AXI4 read address ready.
m_axi_rdata [n-1:0] Input AXI4 read data.
m_axi_rresp [1:0] Input AXI4 read response.
m_axi_rlast Input AXI4 read last.
m_axi_rvalid Input AXI4 read valid.
m_axi_rready Output AXI4 read ready.