SD Host Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example designs target the Trion® T120 BGA576 Development Board. The example design consists of a RISC-V SoC and the SD Host Controller core. The design requires an additional SD daughter card attached to the Trion® T120 BGA576 Development Board.

Note: Efinix uses PmodSD from Digilent as the SD daughter card for the example design.

Figure 1. Standalone Example Design Block Diagram

Run the example code, sdhc.c in the embedded_sw folder to check the multi block read and write operation is working as expected. The UART terminal prints the following message if test is successful:

--- EFX-SD Card Demo ---

Initialize...Done

**************START SPEED TEST*******************
**SD CLOCK SPEED = 50000
**CARD SPEED = 25000 kHz
**CARD SIZE = 7580 Mbyte Total BLOCK = 15523840
**SD BUS WIDTH = 4
**BLOCK SIZE = 512 BUFFER OF BLOCK = 64
**TEST SIZE = 32 kbyte
*************************************************

!!!!Warning it will crash the SD card data!!!!

      ###Push Any Key to Continue###
Tested Block 0/15523840          Write s=629 KByte/s   Read s=514 KByte/s
Tested Block 1024/15523840    Write s=629 KByte/s   Read s=514 KByte/s

Table 1. Example Design Implementation
FPGA	LUTs	Registers	Memory Blocks	Multipliers	f_MAX (MHz)¹		Efinity® Version²
FPGA	LUTs	Registers	Memory Blocks	Multipliers	System Clock	SD Host Clock	Efinity® Version²
T120 BGA576 C4	9,114	9,370	82	4	61	107	2023.2