Watchdog driver API definitions.
- Note
- The watchdog hardware is designed as following :
- There is a shared prescaler provide a periodic tick.
- There is one/multiple counters which increment when the prescaler overflow.
- Each of those counters will have its own "limit" register which will specify when it will generate its own interrupt.
- All counters and the "softPanic" can be cleared together by the software executing a heartbeat.
- Typicaly, the watchdog can be configured to have two counters:
- Counter 0 would provide an interrupt to let's the CPU handle the issue or shutdown the system cleanly.
- Counter 1, configured to trigger after counter 0, would be connected in hardware to reset the whole system in a hard way.