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i2c.c
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6
16
17#include "i2c/i2c.h"
18
19/*----------------------------------------------------------------------------*/
20/* Function implementations */
21/*----------------------------------------------------------------------------*/
22
24{
25 return inst->hwreg->INTERRUPT;
26}
27
29{
30 return inst->hwreg->MASTER_STATUS;
31}
32
34{
35 return inst->hwreg->HIT_CONTEXT;
36}
37
42
44{
45 return inst->hwreg->SLAVE_STATUS;
46}
47
52
53
55{
56 inst->hwreg->SLAVE_OVERRIDE = value;
57}
58
60{
62 inst->hwreg->TIMEOUT = inst->timeout;
63 inst->hwreg->TSU_DATA = inst->tsuDat;
64 inst->hwreg->tLOW = inst->tLow;
65 inst->hwreg->tHIGH = inst->tHigh;
66 inst->hwreg->tBUF = inst->tBuf;
67}
68
73
75{
76 i2c_startMaster(inst);
77}
78
83
85{
86 return (inst->hwreg->MASTER_STATUS & I2C_MASTER_BUSY) !=0 ;
87}
88
94
99
104
106{
107 i2c_stopMaster(inst);
108 while(i2c_checkMasterBusy(inst));
109}
110
115
117{
118 for(int i = 0;i < 3;i++){
119 i2c_recoverMaster(inst);
122 break;
123 }
124 }
125}
126
128{
129 inst->hwreg->RX_ACK = I2C_RX_LISTEN ;
130}
131
136
138{
140}
141
143{
144 inst->hwreg->TX_ACK = 1 | I2C_TX_VALID | I2C_TX_ENABLE;
145}
146
148{
149 while(inst->hwreg->TX_ACK & I2C_TX_VALID);
150}
151
153{
154 while((inst->hwreg->RX_ACK & I2C_RX_VALUE) != 0);
155}
156
158{
159 i2c_txAck(inst);
160 i2c_txAckWait(inst);
161}
162
164{
165 i2c_txNack(inst);
166 i2c_txAckWait(inst);
167}
168
170{
171 return inst->hwreg->RX_DATA & I2C_RX_VALUE;
172}
173
175{
176 return (inst->hwreg->RX_ACK & I2C_RX_VALUE) != 0;
177}
178
180{
181 return (inst->hwreg->RX_ACK & I2C_RX_VALUE) == 0;
182}
183
188
193
194void i2c_setFilterConfig(i2c_instance_t *inst, u32 filterId, u32 value)
195{
196 inst->hwreg->FILTER[filterId].FILTER_CONFIG_0 = value;
197}
198
199void i2c_enableFilter(i2c_instance_t *inst, u32 filterId, u32 config)
200{
201 inst->hwreg->FILTER[filterId].FILTER_CONFIG_0 = config;
202}
203
205{
206 inst->hwreg->INTERRUPT &= ~value ;
207}
208
210{
211 inst->hwreg->INTERRUPT |= value;
212}
213
215{
216 inst->hwreg->INTERRUPT_CLEAR = value;
217}
218
219void i2c_writeData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length) {
220
221 // Send Start Sequence
223 // Send Slave Address (Write Mode)
224 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
225 // Send Register Address (8-bit)
226 TX_AND_CHECK(inst, (regAddr & 0xFF));
227 // Send Data Bytes
228 // Note: In Write mode, we treat all bytes the same (Slave ACKs all of them)
229 for (u32 i = 0; i < length; i++) {
230 TX_AND_CHECK(inst, data[i]);
231 }
232 // Send Stop Sequence
234}
235
236void i2c_writeData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length) {
237 // Send Start Sequence
239 // Send Slave Address (Write Mode)
240 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
241 // Send Register Address High Byte (MSB)
242 TX_AND_CHECK(inst, (regAddr >> 8) & 0xFF);
243 // Send Register Address Low Byte (LSB)
244 TX_AND_CHECK(inst, (regAddr & 0xFF));
245 // Send Data Bytes
246 for (u32 i = 0; i < length; i++) {
247 TX_AND_CHECK(inst, data[i]);
248 }
249 // Send Stop Sequence
251}
252
253void i2c_readData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length) {
254 // Send Start Sequence
256 // Send Slave Address (Write Mode)
257 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
258 // Send Register Address
259 TX_AND_CHECK(inst, (regAddr & 0xFF));
260 // Send Restart Sequence
262 // Send Slave Address (Read Mode)
263 TX_AND_CHECK(inst, inst->slaveAddress | I2C_READ);
264 // Read Loop (Length > 1)
265 if (length > 1) {
266 for (int i = 0; i < length - 1; i++) {
267 i2c_txByte(inst, 0xFF); // Release SDA
268 i2c_txAckBlocking(inst); // Send ACK to request next byte
269 data[i] = i2c_rxData(inst); // Read Data
270 }
271 }
272 // Read Last Byte
273 i2c_txByte(inst, 0xFF); // Release SDA
274 i2c_txNackBlocking(inst); // Send NACK to stop slave transmission
275 data[length - 1] = i2c_rxData(inst); // Read Last Data
276 // Send Stop Sequence
278}
279
280void i2c_readData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length) {
281 // Send Start Sequence
283 // Send Slave Address (Write Mode)
284 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
285 // Send Register Address
286 TX_AND_CHECK(inst, ((regAddr >> 8) & 0xFF));
287 // Send Restart Sequence
289 // Send Slave Address (Read Mode)
290 TX_AND_CHECK(inst, inst->slaveAddress | I2C_READ);
291 // Read Loop (Length > 1)
292 if (length > 1) {
293 for (int i = 0; i < length - 1; i++) {
294 i2c_txByte(inst, 0xFF); // Release SDA
295 i2c_txAckBlocking(inst); // Send ACK to request next byte
296 data[i] = i2c_rxData(inst); // Read Data
297 }
298 }
299 // Read Last Byte
300 i2c_txByte(inst, 0xFF); // Release SDA
301 i2c_txNackBlocking(inst); // Send NACK to stop slave transmission
302 data[length - 1] = i2c_rxData(inst); // Read Last Data
303 // Send Stop Sequence
305}
306
307void i2c_setMux(i2c_instance_t *inst, const uint8_t cr)
308{
309 // u8 outdata;
310
312 i2c_txByte(inst, (0x71<<1)); //Hardcoded to 0x71 Mux for now!
313 i2c_txNackBlocking(inst);
314 // assert(i2c_rxAck(inst)); // Optional check
315
316 i2c_txByte(inst, cr);
317 i2c_txNackBlocking(inst);
318 // assert(i2c_rxAck(inst)); // Optional check
319
321}
i2c_interrupt_t
I2C Enable Interrupt List.
Definition i2c.h:147
void i2c_clearInterruptFlag(i2c_instance_t *inst, i2c_interrupt_t value)
Clears specific I2C interrupt flags.
Definition i2c.c:214
void i2c_startMasterBlocking(i2c_instance_t *inst)
Initiate start condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:89
void i2c_recoverMasterBlocking(i2c_instance_t *inst)
Initiate recover condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:116
void i2c_setMux(i2c_instance_t *inst, const uint8_t cr)
Set I2C MUX control register.
Definition i2c.c:307
void i2c_txAckWait(i2c_instance_t *inst)
Waits until the transmission of an ACK signal is complete over the I2C bus.
Definition i2c.c:147
void i2c_readData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length)
Read data with a 16-bit register address over I2C.
Definition i2c.c:280
void i2c_txAck(i2c_instance_t *inst)
Transmits an ACK signal over I2C.
Definition i2c.c:137
void i2c_restartMasterBlocking(i2c_instance_t *inst)
Initiate restart condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:95
void i2c_txNack(i2c_instance_t *inst)
Transmits an NACK signal over I2C.
Definition i2c.c:142
void i2c_stopMaster(i2c_instance_t *inst)
Initiate stop condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:100
void i2c_writeData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length)
Write data with an 8-bit register address over I2C and check rx ack for each transaction.
Definition i2c.c:219
void i2c_applyConfig(i2c_instance_t *inst)
Apply the software configuration to the hardware.
Definition i2c.c:59
void i2c_txByte(i2c_instance_t *inst, u8 byte)
Transmits a byte of data over I2C.
Definition i2c.c:132
void i2c_enableFilter(i2c_instance_t *inst, u32 filterId, u32 config)
Enables and configures an I2C hardware filter.
Definition i2c.c:199
u32 i2c_getFilteringHit(i2c_instance_t *inst)
Get Filtering Hit.
Definition i2c.c:33
u32 i2c_getSlaveOverride(i2c_instance_t *inst)
Get Slave Override.
Definition i2c.c:48
void i2c_txNackRepeat(i2c_instance_t *inst)
Sends a NACK signal over I2C bus with repeat mode enabled.
Definition i2c.c:189
void i2c_disableInterrupt(i2c_instance_t *inst, i2c_interrupt_t value)
Disables specific I2C interrupts.
Definition i2c.c:204
u32 i2c_rxNack(i2c_instance_t *inst)
Checks if the received ACK signal is detected.
Definition i2c.c:174
u32 i2c_rxAck(i2c_instance_t *inst)
Reads data from I2C receive data register.
Definition i2c.c:179
u32 i2c_checkMasterBusy(i2c_instance_t *inst)
Checks if the I2C master is busy.
Definition i2c.c:84
u32 i2c_getSlaveStatus(i2c_instance_t *inst)
Get Slave Status.
Definition i2c.c:43
void i2c_txAckBlocking(i2c_instance_t *inst)
Sends an ACK signal over the I2C bus and waits until the transmission is complete.
Definition i2c.c:157
void i2c_startMaster(i2c_instance_t *inst)
Initiate start condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:69
void i2c_txByteRepeat(i2c_instance_t *inst, u8 byte)
Sends a byte over I2C bus with repeat mode enabled.
Definition i2c.c:184
void i2c_rxAckWait(i2c_instance_t *inst)
Waits until the reception of an ACK signal is complete over the I2C bus.
Definition i2c.c:152
void i2c_setFilterConfig(i2c_instance_t *inst, u32 filterId, u32 value)
Sets the configuration for an I2C hardware filter.
Definition i2c.c:194
void i2c_setSlaveOverride(i2c_instance_t *inst, u32 value)
Write values to I2C hardware registers.
Definition i2c.c:54
u32 i2c_getMasterStatus(i2c_instance_t *inst)
Get Master Status.
Definition i2c.c:28
void i2c_enableInterrupt(i2c_instance_t *inst, i2c_interrupt_t value)
Enables specific I2C interrupts.
Definition i2c.c:209
void i2c_listenAck(i2c_instance_t *inst)
configures the I2C controller to listen for ACK signals on the receiver (RX) line.
Definition i2c.c:127
u32 i2c_getInterruptFlag(i2c_instance_t *inst)
Get Interrupt Flag.
Definition i2c.c:23
void i2c_readData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length)
Read data with an 8-bit register address over I2C.
Definition i2c.c:253
void i2c_dropMaster(i2c_instance_t *inst)
Drops the current I2C master operation.
Definition i2c.c:111
void i2c_restartMaster(i2c_instance_t *inst)
Initiate restart condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:74
void i2c_txNackBlocking(i2c_instance_t *inst)
Sends an NACK signal over the I2C bus and waits until the transmission is complete.
Definition i2c.c:163
void i2c_writeData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length)
Write data with a 16-bit register address over I2C and check rx ack for each transaction.
Definition i2c.c:236
u32 i2c_getFilteringStatus(i2c_instance_t *inst)
Get Filtering Status.
Definition i2c.c:38
u32 i2c_rxData(i2c_instance_t *inst)
Reads data from I2C receive data register.
Definition i2c.c:169
void i2c_stopMasterBlocking(i2c_instance_t *inst)
Initiate stop condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:105
void i2c_recoverMaster(i2c_instance_t *inst)
Initiate recover condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:79
#define I2C_TX_DISABLE_ON_DATA_CONFLICT
Mask for Disable TX on data conflict *‍/.
Definition i2c.h:62
#define I2C_MASTER_RECOVER_DROPPED
Mask for Master Recover Dropped *‍/.
Definition i2c.h:78
#define I2C_RX_VALUE
Mask for RX value *‍/.
Definition i2c.h:63
#define I2C_TX_ENABLE
Mask for Enable TX *‍/.
Definition i2c.h:60
#define TX_AND_CHECK(inst, byte)
Transmits a single byte over the I2C bus and waits for an ACK response.
Definition i2c.h:119
#define I2C_MASTER_RECOVER
Mask for Master Recover *‍/.
Definition i2c.h:75
#define I2C_MASTER_START
Mask for Master Start *‍/.
Definition i2c.h:72
#define I2C_MASTER_DROP
Mask for Master Drop *‍/.
Definition i2c.h:74
#define I2C_MASTER_STOP_DROPPED
Mask for Master Stop Dropped *‍/.
Definition i2c.h:77
#define I2C_WRITE
Indicate Write Transcation *‍/.
Definition i2c.h:98
#define I2C_TX_VALID
Mask for TX valid bit *‍/.
Definition i2c.h:59
#define I2C_MASTER_BUSY
Mask for Master Busy *‍/.
Definition i2c.h:71
#define I2C_MASTER_START_DROPPED
Mask for Master Start Dropped *‍/.
Definition i2c.h:76
#define I2C_READ
Indicate Read Transcation *‍/.
Definition i2c.h:97
#define I2C_MASTER_STOP
Mask for Master Stop *‍/.
Definition i2c.h:73
#define I2C_TX_REPEAT
Mask for Repeat TX *‍/.
Definition i2c.h:61
#define I2C_RX_LISTEN
Mask for RX listen mode *‍/.
Definition i2c.h:65
I2C driver API definitions.
u32 FILTER_CONFIG_0
Offset +0x00: Primary Filter Config (Addr/Enable) *‍/.
Definition i2c.h:206
u32 TSU_DATA
Address Offset: 0x30 *‍/.
Definition i2c.h:226
u32 SLAVE_OVERRIDE
Address Offset: 0x48 *‍/.
Definition i2c.h:230
u32 tLOW
Address Offset: 0x50 *‍/.
Definition i2c.h:232
u32 MASTER_STATUS
Address Offset: 0x40 *‍/.
Definition i2c.h:228
u32 tHIGH
Address Offset: 0x54 *‍/.
Definition i2c.h:233
i2c_filter_hwreg_t FILTER[3]
Address Offset: 0x8C *‍/.
Definition i2c.h:238
u32 INTERRUPT_CLEAR
Address Offset: 0x24 *‍/.
Definition i2c.h:223
u32 HIT_CONTEXT
Address Offset: 0x80 *‍/.
Definition i2c.h:236
u32 RX_ACK
Address Offset: 0x0C *‍/.
Definition i2c.h:220
u32 TX_DATA
Address Offset: 0x00 *‍/.
Definition i2c.h:217
u32 TX_ACK
Address Offset: 0x04 *‍/.
Definition i2c.h:218
u32 SLAVE_STATUS
Address Offset: 0x44 *‍/.
Definition i2c.h:229
u32 INTERRUPT
Address Offset: 0x20 *‍/.
Definition i2c.h:222
u32 RX_DATA
Address Offset: 0x08 *‍/.
Definition i2c.h:219
u32 tBUF
Address Offset: 0x58 *‍/.
Definition i2c.h:234
u32 SAMPLING_CLOCK_DIVIDER
Address Offset: 0x28 *‍/.
Definition i2c.h:224
u32 FILTER_STATUS
Address Offset: 0x84 *‍/.
Definition i2c.h:237
u32 TIMEOUT
Address Offset: 0x2C *‍/.
Definition i2c.h:225
I2C instance. Holds the software registers and hardware pointer.
Definition i2c.h:259
u32 tBuf
Bus Free Time between STOP and START *‍/.
Definition i2c.h:267
u32 timeout
Timeout Value *‍/.
Definition i2c.h:263
u32 tLow
SCL Low Time *‍/.
Definition i2c.h:265
i2c_hwreg_t * hwreg
Pointer to Hardware Register Map *‍/.
Definition i2c.h:260
u32 tsuDat
Data Setup Time *‍/.
Definition i2c.h:264
u32 tHigh
SCL High Time *‍/.
Definition i2c.h:266
u32 samplingClockDivider
Sampling Clock Divider *‍/.
Definition i2c.h:262
u32 slaveAddress
7-bit Slave Address *‍/
Definition i2c.h:261
uint8_t u8
Definition type.h:26
uint16_t u16
Definition type.h:24
uint32_t u32
Definition type.h:22