RV32 SoC DS UG
High-Perf RV32 SoC DS UG
RV64 SoC DS UG API and Examples
Embedded IDE UG
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i2c.c
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1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6
16
17#include "i2c/i2c.h"
18
19/*----------------------------------------------------------------------------*/
20/* Function implementations */
21/*----------------------------------------------------------------------------*/
22
27
29{
30 return inst->hwreg->INTERRUPT;
31}
32
34{
35 return inst->hwreg->MASTER_STATUS;
36}
37
39{
40 return inst->hwreg->HIT_CONTEXT;
41}
42
47
49{
50 return inst->hwreg->SLAVE_STATUS;
51}
52
57
59{
60 return inst->hwreg->RX_DATA & I2C_RX_VALUE;
61}
62
64{
65 return (inst->hwreg->RX_ACK & I2C_RX_VALUE) != 0;
66}
67
69{
70 return (inst->hwreg->RX_ACK & I2C_RX_VALUE) == 0;
71}
72
74{
75 inst->hwreg->SLAVE_OVERRIDE = value;
76}
77
78void i2c_setFilterConfig(i2c_instance_t *inst, u32 filterId, u32 value)
79{
80 inst->hwreg->FILTER[filterId].FILTER_CONFIG_0 = value;
81}
82
84{
86 inst->hwreg->TIMEOUT = inst->timeout;
87 inst->hwreg->TSU_DATA = inst->tsuDat;
88 inst->hwreg->tLOW = inst->tLow;
89 inst->hwreg->tHIGH = inst->tHigh;
90 inst->hwreg->tBUF = inst->tBuf;
91}
92
97
99{
100 i2c_startMaster(inst);
101}
102
107
109{
110 return (inst->hwreg->MASTER_STATUS & I2C_MASTER_BUSY) !=0 ;
111}
112
118
123
128
130{
131 i2c_stopMaster(inst);
132 while(i2c_checkMasterBusy(inst));
133}
134
139
141{
142 for(int i = 0;i < 3;i++){
143 i2c_recoverMaster(inst);
146 break;
147 }
148 }
149}
150
152{
153 inst->hwreg->RX_ACK = I2C_RX_LISTEN ;
154}
155
157{
158 i2c_sendTxNack(inst);
159 i2c_waitTxAck(inst);
160}
161
163{
164 i2c_sendTxAck(inst);
165 i2c_waitTxAck(inst);
166}
167
172
177
182
187
189{
190 inst->hwreg->TX_ACK = 1 | I2C_TX_VALID | I2C_TX_ENABLE;
191}
192
194{
195 while(inst->hwreg->TX_ACK & I2C_TX_VALID);
196}
197
199{
200 while((inst->hwreg->RX_ACK & I2C_RX_VALUE) != 0);
201}
202
203
204void i2c_enableFilter(i2c_instance_t *inst, u32 filterId, u32 config)
205{
206 inst->hwreg->FILTER[filterId].FILTER_CONFIG_0 = config;
207}
208
210{
211 inst->hwreg->INTERRUPT &= ~value ;
212}
213
215{
216 inst->hwreg->INTERRUPT |= value;
217}
218
220{
221 inst->hwreg->INTERRUPT_CLEAR = value;
222}
223
224void i2c_writeData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length) {
225
226 // Send Start Sequence
228 // Send Slave Address (Write Mode)
229 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
230 // Send Register Address (8-bit)
231 TX_AND_CHECK(inst, (regAddr & 0xFF));
232 // Send Data Bytes
233 // Note: In Write mode, we treat all bytes the same (Slave ACKs all of them)
234 for (u32 i = 0; i < length; i++) {
235 TX_AND_CHECK(inst, data[i]);
236 }
237 // Send Stop Sequence
239}
240
241void i2c_writeData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length) {
242 // Send Start Sequence
244 // Send Slave Address (Write Mode)
245 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
246 // Send Register Address High Byte (MSB)
247 TX_AND_CHECK(inst, (regAddr >> 8) & 0xFF);
248 // Send Register Address Low Byte (LSB)
249 TX_AND_CHECK(inst, (regAddr >> 0) & 0xFF);
250 // Send Data Bytes
251 for (u32 i = 0; i < length; i++) {
252 TX_AND_CHECK(inst, data[i]);
253 }
254 // Send Stop Sequence
256}
257
258void i2c_readData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length) {
259 // Send Start Sequence
261 // Send Slave Address (Write Mode)
262 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
263 // Send Register Address
264 TX_AND_CHECK(inst, (regAddr & 0xFF));
265 // Send Restart Sequence
267 // Send Slave Address (Read Mode)
268 TX_AND_CHECK(inst, inst->slaveAddress | I2C_READ);
269 // Read Loop (Length > 1)
270 if (length > 1) {
271 for (int i = 0; i < length - 1; i++) {
272 i2c_sendTxByte(inst, 0xFF); // Release SDA
273 i2c_sendAckBlocking(inst); // Send ACK to request next byte
274 data[i] = i2c_getRxData(inst); // Read Data
275 }
276 }
277 // Read Last Byte
278 i2c_sendTxByte(inst, 0xFF); // Release SDA
279 i2c_sendNackBlocking(inst); // Send NACK to stop slave transmission
280 data[length - 1] = i2c_getRxData(inst); // Read Last Data
281 // Send Stop Sequence
283}
284
285void i2c_readData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length) {
286 // Send Start Sequence
288 // Send Slave Address (Write Mode)
289 TX_AND_CHECK(inst, inst->slaveAddress | I2C_WRITE);
290 // Send Register Address (High Byte)
291 TX_AND_CHECK(inst, ((regAddr >> 8) & 0xFF));
292 // Send Register Address (Low Byte)
293 TX_AND_CHECK(inst, ((regAddr >> 0) & 0xFF));
294 // Send Restart Sequence
296 // Send Slave Address (Read Mode)
297 TX_AND_CHECK(inst, inst->slaveAddress | I2C_READ);
298 // Read Loop (Length > 1)
299 if (length > 1) {
300 for (int i = 0; i < length - 1; i++) {
301 i2c_sendTxByte(inst, 0xFF); // Release SDA
302 i2c_sendAckBlocking(inst); // Send ACK to request next byte
303 data[i] = i2c_getRxData(inst); // Read Data
304 }
305 }
306 // Read Last Byte
307 i2c_sendTxByte(inst, 0xFF); // Release SDA
308 i2c_sendNackBlocking(inst); // Send NACK to stop slave transmission
309 data[length - 1] = i2c_getRxData(inst); // Read Last Data
310 // Send Stop Sequence
312}
313
314void i2c_setMux(i2c_instance_t *inst, const uint8_t cr)
315{
316 // u8 outdata;
317
319 i2c_sendTxByte(inst, (0x71<<1)); //Hardcoded to 0x71 Mux for now!
321 // assert(i2c_getRxAck(inst)); // Optional check
322
323 i2c_sendTxByte(inst, cr);
325 // assert(i2c_getRxAck(inst)); // Optional check
326
328}
i2c_interrupt_t
I2C Enable Interrupt List.
Definition i2c.h:178
void i2c_clearInterruptFlag(i2c_instance_t *inst, i2c_interrupt_t value)
Clears specific I2C interrupt flags.
Definition i2c.c:219
void i2c_startMasterBlocking(i2c_instance_t *inst)
Initiate start condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:113
void i2c_sendTxAck(i2c_instance_t *inst)
Transmits an ACK signal over I2C.
Definition i2c.c:183
void i2c_recoverMasterBlocking(i2c_instance_t *inst)
Initiate recover condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:140
void i2c_setMux(i2c_instance_t *inst, const uint8_t cr)
Set I2C MUX control register.
Definition i2c.c:314
void i2c_sendNackBlocking(i2c_instance_t *inst)
Sends an NACK signal over the I2C bus and waits until the transmission is complete.
Definition i2c.c:156
void i2c_readData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length)
Read data with a 16-bit register address over I2C.
Definition i2c.c:285
void i2c_restartMasterBlocking(i2c_instance_t *inst)
Initiate restart condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:119
void i2c_stopMaster(i2c_instance_t *inst)
Initiate stop condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:124
void i2c_sendAckBlocking(i2c_instance_t *inst)
Sends an ACK signal over the I2C bus and waits until the transmission is complete.
Definition i2c.c:162
void i2c_writeData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length)
Write data with an 8-bit register address over I2C and check rx ack for each transaction.
Definition i2c.c:224
void i2c_applyConfig(i2c_instance_t *inst)
Apply the software configuration to the hardware.
Definition i2c.c:83
void i2c_sendTxByte(i2c_instance_t *inst, u8 byte)
Transmits a byte of data over I2C.
Definition i2c.c:178
void i2c_sendTxNack(i2c_instance_t *inst)
Transmits an NACK signal over I2C.
Definition i2c.c:188
u32 i2c_getRxData(i2c_instance_t *inst)
Reads data from I2C receive data register.
Definition i2c.c:58
void i2c_enableFilter(i2c_instance_t *inst, u32 filterId, u32 config)
Enables and configures an I2C hardware filter.
Definition i2c.c:204
u32 i2c_getFilteringHit(i2c_instance_t *inst)
Get Filtering Hit.
Definition i2c.c:38
u32 i2c_getSlaveOverride(i2c_instance_t *inst)
Get Slave Override.
Definition i2c.c:53
void i2c_disableInterrupt(i2c_instance_t *inst, i2c_interrupt_t value)
Disables specific I2C interrupts.
Definition i2c.c:209
void i2c_sendTxNackRepeat(i2c_instance_t *inst)
Sends a NACK signal over I2C bus with repeat mode enabled.
Definition i2c.c:173
u32 i2c_checkMasterBusy(i2c_instance_t *inst)
Checks if the I2C master is busy.
Definition i2c.c:108
u32 i2c_getSlaveStatus(i2c_instance_t *inst)
Get Slave Status.
Definition i2c.c:48
void i2c_startMaster(i2c_instance_t *inst)
Initiate start condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:93
u32 i2c_getRxNack(i2c_instance_t *inst)
Checks if the received ACK signal is detected.
Definition i2c.c:63
void i2c_setFilterConfig(i2c_instance_t *inst, u32 filterId, u32 value)
Sets the configuration for an I2C hardware filter.
Definition i2c.c:78
void i2c_waitTxAck(i2c_instance_t *inst)
Waits until the transmission of an ACK signal is complete over the I2C bus.
Definition i2c.c:193
void i2c_setSlaveOverride(i2c_instance_t *inst, u32 value)
Write values to I2C hardware registers.
Definition i2c.c:73
void i2c_waitRxAck(i2c_instance_t *inst)
Waits until the reception of an ACK signal is complete over the I2C bus.
Definition i2c.c:198
u32 i2c_getMasterStatus(i2c_instance_t *inst)
Get Master Status.
Definition i2c.c:33
void i2c_enableInterrupt(i2c_instance_t *inst, i2c_interrupt_t value)
Enables specific I2C interrupts.
Definition i2c.c:214
void i2c_listenAck(i2c_instance_t *inst)
Configures the I2C controller to listen for ACK signals on the receiver (RX) line.
Definition i2c.c:151
u32 i2c_getInterruptFlag(i2c_instance_t *inst)
Get Interrupt Flag.
Definition i2c.c:23
void i2c_readData_b(i2c_instance_t *inst, u8 regAddr, u8 *data, u32 length)
Read data with an 8-bit register address over I2C.
Definition i2c.c:258
void i2c_dropMaster(i2c_instance_t *inst)
Drops the current I2C master operation.
Definition i2c.c:135
void i2c_restartMaster(i2c_instance_t *inst)
Initiate restart condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:98
void i2c_writeData_w(i2c_instance_t *inst, u16 regAddr, u8 *data, u32 length)
Write data with a 16-bit register address over I2C and check rx ack for each transaction.
Definition i2c.c:241
void i2c_sendTxByteRepeat(i2c_instance_t *inst, u8 byte)
Sends a byte over I2C bus with repeat mode enabled.
Definition i2c.c:168
u32 i2c_getFilteringStatus(i2c_instance_t *inst)
Get Filtering Status.
Definition i2c.c:43
void i2c_stopMasterBlocking(i2c_instance_t *inst)
Initiate stop condition for I2C master mode and waits until the operation is complete.
Definition i2c.c:129
void i2c_recoverMaster(i2c_instance_t *inst)
Initiate recover condition for I2C master mode and sets the dropped status if necessary.
Definition i2c.c:103
u32 i2c_getRxAck(i2c_instance_t *inst)
Reads Acknowledge signal from I2C receive data register.
Definition i2c.c:68
u32 i2c_getInterruptEnable(i2c_instance_t *inst)
Get Interrupt Enable.
Definition i2c.c:28
#define I2C_TX_DISABLE_ON_DATA_CONFLICT
Mask for Disable TX on data conflict.
Definition i2c.h:93
#define I2C_MASTER_RECOVER_DROPPED
Mask for Master Recover Dropped.
Definition i2c.h:109
#define I2C_RX_VALUE
Mask for RX value.
Definition i2c.h:94
#define I2C_TX_ENABLE
Mask for Enable TX.
Definition i2c.h:91
#define TX_AND_CHECK(inst, byte)
Transmits a single byte over the I2C bus and waits for an ACK response.
Definition i2c.h:150
#define I2C_MASTER_RECOVER
Mask for Master Recover.
Definition i2c.h:106
#define I2C_MASTER_START
Mask for Master Start.
Definition i2c.h:103
#define I2C_MASTER_DROP
Mask for Master Drop.
Definition i2c.h:105
#define I2C_MASTER_STOP_DROPPED
Mask for Master Stop Dropped.
Definition i2c.h:108
#define I2C_WRITE
Indicate Write Transcation.
Definition i2c.h:129
#define I2C_TX_VALID
Mask for TX valid bit.
Definition i2c.h:90
#define I2C_MASTER_BUSY
Mask for Master Busy.
Definition i2c.h:102
#define I2C_MASTER_START_DROPPED
Mask for Master Start Dropped.
Definition i2c.h:107
#define I2C_READ
Indicate Read Transcation.
Definition i2c.h:128
#define I2C_MASTER_STOP
Mask for Master Stop.
Definition i2c.h:104
#define I2C_TX_REPEAT
Mask for Repeat TX.
Definition i2c.h:92
#define I2C_RX_LISTEN
Mask for RX listen mode.
Definition i2c.h:96
I2C driver API definitions.
u32 FILTER_CONFIG_0
Offset +0x00: Primary Filter Config (Addr/Enable).
Definition i2c.h:237
u32 TSU_DATA
Address Offset: 0x30.
Definition i2c.h:257
u32 SLAVE_OVERRIDE
Address Offset: 0x48.
Definition i2c.h:261
u32 tLOW
Address Offset: 0x50.
Definition i2c.h:263
u32 MASTER_STATUS
Address Offset: 0x40.
Definition i2c.h:259
u32 tHIGH
Address Offset: 0x54.
Definition i2c.h:264
i2c_filter_hwreg_t FILTER[3]
Address Offset: 0x8C.
Definition i2c.h:269
u32 INTERRUPT_CLEAR
Address Offset: 0x24.
Definition i2c.h:254
u32 HIT_CONTEXT
Address Offset: 0x80.
Definition i2c.h:267
u32 RX_ACK
Address Offset: 0x0C.
Definition i2c.h:251
u32 TX_DATA
Address Offset: 0x00.
Definition i2c.h:248
u32 TX_ACK
Address Offset: 0x04.
Definition i2c.h:249
u32 SLAVE_STATUS
Address Offset: 0x44.
Definition i2c.h:260
u32 INTERRUPT
Address Offset: 0x20.
Definition i2c.h:253
u32 RX_DATA
Address Offset: 0x08.
Definition i2c.h:250
u32 tBUF
Address Offset: 0x58.
Definition i2c.h:265
u32 SAMPLING_CLOCK_DIVIDER
Address Offset: 0x28.
Definition i2c.h:255
u32 FILTER_STATUS
Address Offset: 0x84.
Definition i2c.h:268
u32 TIMEOUT
Address Offset: 0x2C.
Definition i2c.h:256
I2C instance. Holds the software registers and hardware pointer.
Definition i2c.h:290
u32 tBuf
Bus Free Time between STOP and START.
Definition i2c.h:298
u32 timeout
Timeout Value.
Definition i2c.h:294
u32 tLow
SCL Low Time.
Definition i2c.h:296
i2c_hwreg_t * hwreg
Pointer to Hardware Register Map.
Definition i2c.h:291
u32 tsuDat
Data Setup Time.
Definition i2c.h:295
u32 tHigh
SCL High Time.
Definition i2c.h:297
u32 samplingClockDivider
Sampling Clock Divider.
Definition i2c.h:293
u32 slaveAddress
7-bit Slave Address
Definition i2c.h:292
uint8_t u8
Definition type.h:30
uint16_t u16
Definition type.h:28
uint32_t u32
Definition type.h:26