Register bitmasks and offsets.
I2C Mode Control Register Bitmasks | |
| #define | I2C_MODE_CPOL (1 << 0) |
| I2C Clock Polarity Mask. | |
| #define | I2C_MODE_CPHA (1 << 1) |
| I2C Clock Phase Mask. | |
I2C TX/RX and Status Register Bitmasks | |
| #define | I2C_TX_VALUE (0xFF) |
| Mask for TX value. | |
| #define | I2C_TX_VALID (1 << 8) |
| Mask for TX valid bit. | |
| #define | I2C_TX_ENABLE (1 << 9) |
| Mask for Enable TX. | |
| #define | I2C_TX_REPEAT (1 << 10) |
| Mask for Repeat TX. | |
| #define | I2C_TX_DISABLE_ON_DATA_CONFLICT (1 << 11) |
| Mask for Disable TX on data conflict. | |
| #define | I2C_RX_VALUE (0xFF) |
| Mask for RX value. | |
| #define | I2C_RX_VALID (1 << 8) |
| Mask for RX valid bit. | |
| #define | I2C_RX_LISTEN (1 << 9) |
| Mask for RX listen mode. | |
I2C Master/Slave Status Register Bitmasks | |
| #define | I2C_MASTER_BUSY (1 << 0) |
| Mask for Master Busy. | |
| #define | I2C_MASTER_START (1 << 4) |
| Mask for Master Start. | |
| #define | I2C_MASTER_STOP (1 << 5) |
| Mask for Master Stop. | |
| #define | I2C_MASTER_DROP (1 << 6) |
| Mask for Master Drop. | |
| #define | I2C_MASTER_RECOVER (1 << 7) |
| Mask for Master Recover. | |
| #define | I2C_MASTER_START_DROPPED (1 << 9) |
| Mask for Master Start Dropped. | |
| #define | I2C_MASTER_STOP_DROPPED (1 << 10) |
| Mask for Master Stop Dropped. | |
| #define | I2C_MASTER_RECOVER_DROPPED (1 << 11) |
| Mask for Master Recover Dropped. | |
| #define | I2C_SLAVE_STATUS_IN_FRAME (1 << 0) |
| Mask for the transaction is in progress. | |
| #define | I2C_SLAVE_STATUS_SDA (1 << 1) |
| Mask for Slave's current state of SDA Line. | |
| #define | I2C_SLAVE_STATUS_SCL (1 << 2) |
| Mask for Slave's current state of SCL Line. | |
| #define | I2C_SLAVE_OVERRIDE_SDA (1 << 1) |
| Mask for Force Slave SDA line. | |
| #define | I2C_SLAVE_OVERRIDE_SCL (1 << 2) |
| Mask for Force Slave SCL line. | |
I2C Filter Configuration Bitmasks | |
| #define | I2C_FILTER_7_BITS (0) |
| Filter setting for 7 bits. | |
| #define | I2C_FILTER_10_BITS (1 << 14) |
| Filter setting for 10 bits. | |
| #define | I2C_FILTER_ENABLE (1 << 15) |
| Filter Enable. | |
I2C Read/Write Definitions | |
| #define | I2C_READ 0x01 |
| Indicate Read Transcation. | |
| #define | I2C_WRITE 0x00 |
| Indicate Write Transcation. | |
I2C TX and Check Macro | |
| #define | TX_AND_CHECK(inst, byte) |
| Transmits a single byte over the I2C bus and waits for an ACK response. | |
| #define I2C_FILTER_10_BITS (1 << 14) |
| #define I2C_FILTER_7_BITS (0) |
| #define I2C_FILTER_ENABLE (1 << 15) |
| #define I2C_MASTER_BUSY (1 << 0) |
| #define I2C_MASTER_DROP (1 << 6) |
| #define I2C_MASTER_RECOVER (1 << 7) |
| #define I2C_MASTER_RECOVER_DROPPED (1 << 11) |
| #define I2C_MASTER_START (1 << 4) |
| #define I2C_MASTER_START_DROPPED (1 << 9) |
| #define I2C_MASTER_STOP (1 << 5) |
| #define I2C_MASTER_STOP_DROPPED (1 << 10) |
| #define I2C_MODE_CPHA (1 << 1) |
| #define I2C_MODE_CPOL (1 << 0) |
| #define I2C_READ 0x01 |
| #define I2C_RX_LISTEN (1 << 9) |
| #define I2C_RX_VALID (1 << 8) |
| #define I2C_RX_VALUE (0xFF) |
| #define I2C_SLAVE_OVERRIDE_SCL (1 << 2) |
| #define I2C_SLAVE_OVERRIDE_SDA (1 << 1) |
| #define I2C_SLAVE_STATUS_IN_FRAME (1 << 0) |
| #define I2C_SLAVE_STATUS_SCL (1 << 2) |
| #define I2C_SLAVE_STATUS_SDA (1 << 1) |
| #define I2C_TX_DISABLE_ON_DATA_CONFLICT (1 << 11) |
| #define I2C_TX_ENABLE (1 << 9) |
| #define I2C_TX_REPEAT (1 << 10) |
| #define I2C_TX_VALID (1 << 8) |
| #define I2C_TX_VALUE (0xFF) |
| #define I2C_WRITE 0x00 |
| #define TX_AND_CHECK | ( | inst, | |
| byte ) |
#include <i2c.h>
Transmits a single byte over the I2C bus and waits for an ACK response.
| inst | Pointer to I2C instance. |
| byte | The byte to be transmitted. Holds the software registers and hardware pointer. |