Ports
| Port | Direction | Description |
|---|---|---|
| clk | Input | IP core clock consumed by controller logics. 100 MHz. |
| reset_n | Input | IP core reset signal. |
| clk_byte_HS | Input | MIPI RX parallel clock. This is a HS mode transmission clock. |
| reset_byte_HS_n | Input | MIPI RX parallel clock reset signal. |
| Port | Direction | Description |
|---|---|---|
| Rx_LP_CLK_P | Input | LP mode RX clock single-ended P signal. |
| Rx_LP_CLK_N | Input | LP mode RX clock single-ended N signal. |
| Rx_HS_enable_C | Output | Signal to enable HS mode clock lane. |
| LVDS_termen_C | Output | Signal to enable HS mode clock lane termination . |
| Rx_LP_D_P [NUM_DATA_LANE-1:0] | Input | LP mode RX data single-ended P signal. |
| Rx_LP_D_N [NUM_DATA_LANE-1:0] | Input | LP mode RX data single-ended N signal. |
| Rx_HS_D_0 [7:0] | Input | HS mode differential lane 0 data bus. |
| Rx_HS_D_1 [7:0] | Input | HS mode differential lane 1 data bus. |
| Rx_HS_D_2 [7:0] | Input | HS mode differential lane 2 data bus. |
| Rx_HS_D_3 [7:0] | Input | HS mode differential lane 3 data bus. |
| Rx_HS_D_4 [7:0] | Input | HS mode differential lane 4 data bus. |
| Rx_HS_D_5 [7:0] | Input | HS mode differential lane 5 data bus. |
| Rx_HS_D_6 [7:0] | Input | HS mode differential lane 6 data bus. |
| Rx_HS_D_7 [7:0] | Input | HS mode differential lane 7 data bus. |
| Rx_HS_enable_D [NUM_DATA_LANE-1:0] | Output | Signal to enable HS mode data lane. |
| LVDS_termen_D [NUM_DATA_LANE-1:0] | Output | Signal to enable HS mode data lane termination. |
| fifo_rd_enable [NUM_DATA_LANE-1:0] | Output | Rx HS mode data lane FIFO read enable signal. |
| fifo_rd_empty [NUM_DATA_LANE-1:0] | Input | Rx HS mode data lane FIFO empty signal. |
| DLY_enable_D [NUM_DATA_LANE-1:0] | Output | Reserved port. |
| DLY_inc_D [NUM_DATA_LANE-1:0] | Output | Reserved port. |
| u_dly_enable_D [NUM_DATA_LANE-1:0] | Input | Reserved port. Tie the signal to zero. |
| u_dly_inc_D [NUM_DATA_LANE-1:0] | Input | Reserved port. Tie the signal to zero. |
| Tx_LP_D_P | Output | LP mode TX data single-ended P signal for bidirectional data lane. |
| Tx_LP_D_P_OE | Output | Output enable for LP mode TX data single-ended P signal for bidirectional data lane. |
| Tx_LP_D_N_OE | Output | Output enable for LP mode TX data single-ended N signal for bidirectional data lane. |
| Tx_LP_D_N | Output | LP mode TX data single-ended N signal for bidirectional data lane. |
| Port | Direction | Description |
|---|---|---|
| RxUlpsClkNot | Output | Receive ULPS on Clock Lane. This active-low signal is asserted to
indicate that the clock lane module has entered the ULPS due to the
detection of a request to enter the ULPS. |
| RxUlpsActiveClkNot | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. |
| RxUlpsEsc [NUM_DATA_LANE-1:0] | Output | Escape ULPS. This active-high signal is asserted to indicate that
the lane module has entered the ULPS, due to the detection of a
received ULPS command. |
| RxUlpsActiveNot [NUM_DATA_LANE-1:0] | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. |
| RxLPDTEsc [NUM_DATA_LANE-1:0] | Output | Escape LP Data Receive Mode. This active-high signal is asserted
to indicate that the lane module is in LP data receive
mode. |
| RxValidEsc [NUM_DATA_LANE-1:0] | Output | Escape LP Data Receive Mode. This active-high signal is asserted
to indicate that the lane module is in LP data receive
mode. |
| RxStopState [NUM_DATA_LANE-1:0] | Output | Lane in Stop State. This active-high signal indicates that the
lane module is currently in stop state. |
| RxDataEsc_0 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_0[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_1 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_1[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_2 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_2[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_3 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_3[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_4 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_4[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_5 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_5[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_6 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_6[0] was received first. Data is transferred on rising
edges of clk. |
| RxDataEsc_7 [7:0] | Output | Escape Mode Receive Data. This is the eight-bit escape mode LP
data received by the lane module. The signal connected to
RxDataEsc_7[0] was received first. Data is transferred on rising
edges of clk. |
| RxTriggerEsc [3:0] | Output | EscapeMode Receive Trigger. These active high signals indicate
that a trigger event has been received. The asserted RxTriggerEsc
signal remains active until a stop state is detected on the lane
interconnect. Applicable to bidirectional mode
only. RxTriggerEsc[0] corresponds to reset-trigger.
RxTriggerEsc[1] corresponds to entry sequence for HS test
mode trigger. RxTriggerEsc[2] corresponds to unknown-4
trigger. RxTriggerEsc[3] corresponds to unknown-5
trigger. |
| RxErrEsc [NUM_DATA_LANE-1:0] | Output | Escape Entry Error. If an unrecognized escape entry command is
received in LP mode, this active-high signal is asserted and remains
asserted until the next transaction starts, so that the protocol can
properly process the error. |
| RxErrControl [NUM_DATA_LANE-1:0] | Output | Control Error. This active-high signal is asserted when an
incorrect line state sequence is detected in LP and ALP modes. Once
asserted, this signal remains asserted until the next transaction
starts, so that the protocol can properly process the
error. |
| RxErrSotSyncHS [NUM_DATA_LANE-1:0] | Output | Start-of-Transmission Synchronization Error. If the HS SoT leader
sequence is corrupted in a way that proper synchronization cannot be
expected, this active-high signal is asserted for one cycle of
RxWordClkHS. When ErrSotSyncHS is asserted, RxSyncHS,
ErrSotHS, andRxValidHS is not asserted. |
| RxDataHS_0 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_1 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_2 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_3 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_4 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_5 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_6 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxDataHS_7 [7:0] | Output | HS Receive Data. High-speed data received by the lane
module. |
| RxValidHS [NUM_DATA_LANE-1:0] | Output | HS Receive Data Valid. This active-high signal indicates that the
lane module is driving data to the protocol layer on the RxDataHS
output. |
| RxActiveHS [NUM_DATA_LANE-1:0] | Output | HS Reception Active. This active-high signal indicates that the
lane module is actively receiving a HS transmission from the lane
interconnect. |
| RxSyncHS [NUM_DATA_LANE-1:0] | Output | Receiver Synchronization Observed. This active-high signal
indicates that the lane module has seen an appropriate
synchronization event. |
| RxSkewCalHS [NUM_DATA_LANE-1:0] | Output | HS Receive Skew Calibration. This optional active-high signal
indicates that the high speed deskew burst is being
received. |
| TxRequestEsc | Input | Escape Mode Transmit Request. This active-high signal is used to
request escape sequences. |
| TxTriggerEsc [3:0] | Input | Escape Mode Receive Trigger. These active high signals indicate
that a trigger event has been received. The asserted TxTriggerEsc
signal remains active until a stop state is detected on the lane
interconnect. Applicable to bidirectional mode
only. TxTriggerEsc[0] corresponds to
reset-trigger. TxTriggerEsc[1] corresponds to entry
sequence for HS test mode trigger. TxTriggerEsc[2]
corresponds to unknown-4 trigger. TxTriggerEsc[3]
corresponds to unknown-5 trigger. |
| TxUlpsEsc | Input | Escape Mode Transmit ULPS. This active-high signal is asserted
with TxRequestEsc to cause the lane module to enter the
ULPS. Applicable to bidirectional mode only. |
| TxUlpsExit | Input | Transmit ULPS Exit Sequence. This active-high signal is asserted
when ULPS is active and the protocol is ready to leave
ULPS. Applicable to bidirectional mode only. |
| TxLpdtEsc | Input | Escape Mode Transmit LP Data. This active-high signal is asserted
with TxRequestEsc to cause the lane module to enter LP data
transmission mode. Applicable to bidirectional mode
only. |
| TxDataEsc [7:0] | Input | Escape Mode Transmit Data. This is the eight bit Escape Mode data
to be transmitted in LP data transmission mode. The signal connected
to TxDataEsc[0] is transmitted first. Data is captured on rising
edges of clk. Applicable to bidirectional mode
only. |
| TxValidEsc | Input | Escape Mode Transmit Data Valid. This active-high signal
indicates that the protocol is driving valid data on TxDataEsc to be
transmitted. Applicable to bidirectional mode
only. |
| TxReadyEsc | Output | Escape Mode Transmit Ready. This active-high signal indicates
that TxDataEsc is accepted bythe lane module to be serially
transmitted. TxReadyEsc is valid on rising edges of
TxClkEsc. Applicable to bidirectional mode
only. |
| TxStopState | Output | Lane in Stop State. This active-high signal indicates that the
lane module is in stop state. Applicable to bidirectional
mode only. |
| TxUlpsActiveNot | Output | ULPS (not) Active. This active-low signal is asserted to indicate
that the lane is in ULPS. Applicable to bidirectional mode
only. |
| Turnaround_timeout | Output | Indicates that there is no acknowledgement from the RX D-PHY for the
turnaround request and TX D-PHY ends the turnaround request.
Applicable to bidirectional mode only. |
| TurnRequest | Input | Turnaround Request. This active high signal is used to indicate
that the protocol desires to initiate a bidirectional data lane
turnaround, to allow the other side to begin transmissions.
TurnRequest is valid on rising edge of clk. TurnRequest is only
meaningful for a bidirectional data lane module that is currently
the transmitter (Direction=0). If the bidirectional data lane module
is in receive mode (Direction=1), this signal is ignored. A
low-to-high transition on TurnRequest can only happen when Stopstate
is asserted. Applicable to bidirectional mode
only. |
| TurnRequest_done | Output | Indicates that the RX D-PHY acknowledges the bus turnaround or
timeout. If this signal is high together with turnaround timeout, it
indicates that there is no acknowledgement from the RX on the turnaround
request. Applicable to bidirectional mode only. |