MIPI D-PHY RX Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example design targets the Titanium Ti60 F225 Development Board. The design instantiates both MIPI D-PHY TX Controller and MIPI D-PHY RX Controller cores. This design requires a female-to-female QTE header cable.

The PPI signal generator FSM generates a data and sends back the data through the MIPI D-PHY TX Controller and MIPI D-PHY RX Controller. The PPI signal generator FSM compares the sent and received data, and outputs the results using the board LEDs.

Figure 1. MIPI D-PHY RX Controller Core Example Design

After power-up, LEDs D19 and D18 turn on if the received data and the generated data matches. The RX clock to RX data skew can vary from board to board, therefore, there is a possibility that the RX clock might not be able to capture the RX data correctly. In this case, the LEDs do not turn on. Use the Static Mode Delay Setting in the Interface Designer for the mipi_dphy_rx_clk to adjust the delay up or down.

Table 1. Example Design Implementation
FPGA Data Lane Logic and Adders Flip-flops Memory Blocks DSP48 Blocks fMAX (MHz)1 Efinity® Version2
clk1 clk2 clk3
Ti60 F225 C4 Unidirectional 1,632 783 0 0 295 331 340 2021.2
Bidirectional 1,931 913 0 0 317 353 331 2021.2
  • clk1—mipi_clk
  • clk2—mipi_dphy_rx_clk_CLKOUT
  • clk3—mipi_dphy_tx_SLOWCLK
1 Using default parameter settings.
2 Using Verilog HDL.