Resource Utilization and Performance

Note: The resources and performance values provided are based on some of the supported FPGAs. These values are just guidance and may change depending on the device resource utilization, design congestion, and user design.

Table 2. Titanium Resource Utilization and Performance
FPGA	Data Lane	Logic and Adders	Flip-flops	Memory Blocks	DSP48 Blocks	f_MAX (MHz)¹		Efinity® Version²
FPGA	Data Lane	Logic and Adders	Flip-flops	Memory Blocks	DSP48 Blocks	clk	clk_byte_HS	Efinity® Version²
Ti60 F225 C4	Unidirectional	1,053	567	0	0	401	471	2021.2
Ti60 F225 C4	Bidirectional	1,260	629	0	0	361	364	2021.2

¹ Using default parameter settings.

² Using Verilog HDL.