Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| July 2025 | 3.4 | 5.14 | Corrected on Interrupt Status Register in Control Status Registers
R/W access attribute table. (DOC-2609) Added more details on the
Video Timing Parameter Definition table in the Video Timing
Parameters topic. Corrected the frame_num port description
in Video Interface table. (DOC-2605) |
| June 2025 | 3.3 | 5.12 | Correct description of static delay adjustment in example design. |
| May 2025 | 3.2 | 5.12 | Updated example design. (SIP-891) Example Design IO bank update
(HVIO 3.3V). (SIP-907) Updated default parameter value.
(SIP-910) Updated Customizing the MIPI CSI-2 TX Controller. Added description on debug port for
ready_to_xmit and init_skewcal_done in table Debug
Interface. Updated observation after downloading
bitstream and Example Design Implementation table in Example
Design. Updated Reset Sequence and Initialization topic.
(DOC-2485) |
| March 2025 | 3.1 | 5.11 | Updated Interleaved Data Transmission Waveform (Per-Frame) and Interleaved Data Transmission Waveform (Per-Horizontal Line). (DOC-2442) |
| January 2025 | 3.0 | 5.11 | Updated Figure Video Timing Waveform (Vertical), Interleaved Data
Transmission Waveform (Per-Frame), and Interleaved Data Transmission
Waveform (Per-Horizontal Line). (SIP-823) Added note in Table: Video
Interface in Ports topic for user to fully utilize the pixel data
bus. (SIP-819) Added description for DPHY Clock Mode and
Enable Extra Bit on Virtual Channel in Table 1. (DOC-2307) Example design update to align with MIPI Utility
change (DOC-1783). (SIP-792) |
| December 2024 | 2.9 | 5.10 | Added debug ports for internal signal observation and monitoring in
Ports and Customizing the MIPI CSI-2 TX Controller. (SIP-580) Added
section Interleaved Data Transmission with Virtual Channels.
(SIP-784) |
| November 2024 | 2.8 | 5.9 | Added Topaz in Features and Device Support. (DOC-2102) Added IP
Version in Revision History. (DOC-2185) Soft DPHY 1.5Gbps
performance improvement. (SIP-614) |
| September 2024 | 2.7 | – | Updated Table 3. (DOC-2109) |
| September 2024 | 2.6 | – |
Added 8 lanes support in Features and Table 1. (SIP-677)
Updated pixel data[63:0] in Figure 1.
Removed data type RGB666 from Table 1. (DOC-2068)
Updated tCLK_PRE and tCLK_POST in Table 1. (DOC-2078)
|
| July 2024 | 2.5 | – | Fixed typo in Table 4. (DOC-2004) |
| June 2024 | 2.4 | – | Updated Pixel FIFO depth requirement in table MIPI CSI-2 TX
Controller Core Parameter. (SIP-570) Revised supported lane number
in Features and in table MIPI CSI-2 RX Controller Core Parameter.
(SIP-578) Added Reset Sequence and Initialization
sub-section. |
| March 2024 | 2.3 | – | Added important note in Testbench regarding using default parameters
options only. (DOC-1781) Added testbench file for Modelsim and Aldec
simulation model support. (DOC-1782) Updated content and
topic title Minimum Horizontal Blanking Per Line to Minimum
Horizontal Blanking Per Line Requirement. |
| October 2023 | 2.2 | – |
Updated MIPI video data format tables to include RGB information.
(DOC-1474)
|
| September 2023 | 2.1 | – | Updated Minimum Horizontal Blanking Per Line formula and example. |
| August 2023 | 2.0 | – | Updated Video Timing Waveform (Horizontal) figure and added Minimum Horizontal Blanking Per Line section. (DOC-1414) |
| July 2023 | 1.9 | – | Added more description for Accurate and Generic image frame modes. (DOC-1343) |
| June 2023 | 1.8 | – |
Corrected hsync_vcx and vsync_vcx signal directions.
(DOC-1341)
Added Device Support and release notes sections. (DOC-1234)
Updated supported data rate. (DOC-1217)
Updated port descriptions.
Added RAW16, RAW20, RAW24, and RAW28 format support.
Updated MIPI Parallel Clock Frequency, IP Core Clock Frequency,
Pixel Data FIFO Depth Size, Pack Type40, Pack Type48, Pack Type56,
Pack Type64 parameters.
Improved Interrupt Enable Register Definition descriptions.
Editorial changes.
|
| February 2023 | 1.7 | – | Added note about the resource and performance values in the resource and utilization table are for guidance only. |
| August 2022 | 1.6 | – | Updated Control Status Register note. (DOC-898) |
| August 2022 | 1.5 | – | Added MIPI RX Video Data Formats. Added video parameters
waveform, and port clock domains. (DOC-819) |
| January 2022 | 1.4 | – | Improved description about CSR is accessed through AXI4-Lite
interface. (DOC-690) Corrected interrupt status register width and
improved D-PHY stop state status description.
(DOC-697) Updated resource utilization table.
(DOC-700) |
| December 2021 | 1.3 | – | Added simulation testbench. Added new IP manager
parameters. Added new ports. |
| November 2021 | 1.2 | – | Added support for 8 data lanes. (DOC-604) |
| October 2021 | 1.1 | – | Added note to state that the fMAX in Resource Utilization
and Performance, and Example Design Implementation tables were based on
default parameter settings. Updated design example target board to
production Titanium Ti60 F225 Development Board and updated
Resource Utilization and Performance, and Example Design
Implementation tables. (DOC-553) |
| June 2021 | 1.0 | – | Initial release. |