Customizing the MIPI CSI-2 TX Controller
The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.
| Name | Option | Description |
|---|---|---|
| tLPX (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 50 |
| tINIT (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
100,000 |
| Data Lanes | 1, 2, 4 | Number of data lanes Default: 4 |
| MIPI Parallel Clock Frequency | 10 - 187 | MIPI parallel clock (clk_byte_HS) frequency in MHz to support
data rate of 80 Mbps to 1,500 Mbps. Default: 187 |
| IP Core Clock Frequency | 40 - 100 | IP core clock frequency in MHz Default: 100 |
| DPHY Clock Mode | continuous, discontinuous | To enable discontinuous or continuous HS clock. Continuous
refers to the HS byte clock continuously running during LP or HS
mode. Discontinuous refers to the HS byte clock in
stopped condition during LP mode and in running condition during
HS mode. Default: Continuous |
| Pixel Data FIFO Depth Size | 256 - 8192 | FIFO depth size to store the pixel packet data (set to power of 2
value). Minimum FIFO depth required > horizontal_pixel
(HACT) x bits_per_pixel / 64 Default:
1024 |
| Image Frame Mode | GENERIC, ACCURATE | Selects frame mode. Generic mode: Frame format without
accurate synchronization timing via Line Start and Line
End. Accurate mode: Frame format with accurate
synchronization timing via Line Start and Line
End. Default: Generic |
| tLP_EXIT (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 100 |
| tCLK_ZERO (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 400 |
| tCLK_TRAIL (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 80 |
| tCLK_PRE (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 10 |
| tCLK_POST (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding 52
UI). Default: 455 |
| tCLK_PREPARE (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 50 |
| tWAKEUP (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default:
1000 |
| tHS_ZERO (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Default: 262 |
| tHS_TRAIL (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI). Actual = tHS_TRAIL_NS + 4UI or 8UI (whichever
bigger) Default: 60 |
| tHS_EXIT (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns. Default: 100 |
| tHS_PREPARE (ns) | Values according to MIPI D-PHY specifications. | Soft D-PHY timing parameter in ns (value before adding
UI).. Default: 40 |
| Pack Type 40 | Enable, Disable | Enables the controller to pack RAW10, RAW20, YUV_420_10, and
YUV_422_10 data type.1 Default: Enable |
| Pack Type 48 | Enable, Disable | Enables the controller to pack RAW6, RAW12, RAW24, RGB888, and
YUV_420_8_legacy data type.1 Default: Enable |
| Pack Type 56 | Enable, Disable | Enables the controller to pack RAW7, RAW14, and RAW28.1 Default: Enable |
| Pack Type 64 | Enable, Disable | Enables the controller to pack RAW8, RAW16, RGB444, RGB565,
RGB555, YUV_422_8, YUV_420_8, generic long packet, user define
8-bit, and embedded 8-bit non image packet.1 Default: Enable |
| Enable Extra Bits on Virtual Channel | Enable, Disable | Enable - 16 virtual channels are available. Disable - only 4
virtual channels are available. Default:
Disable |
| MIPI_CSI2_TX_ DEBUG |
Enable, Disable | Enables debug ports for internal signal observation and
monitoring. Default: Disable |
1 Only enable the pack
type that you are using to save logic resources.