MIPI CSI-2 TX Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board.

Important: tested the example design generated with the default parameter options only.

The example design targets the Titanium Ti60 F225 Development Board. The design instantiates both MIPI CSI-2 TX and RX Controller cores. This design requires a QTE header-compatible cable.

The design generates an image and sends the image data to the camera image checker through the MIPI CSI-2 TX Controller. The data is then sent through a hardware loopback on the board using a 4-lane MIPI interface to the MIPI CSI-2 RX Controller. The camera image checker compares the data received with the one created by the image generator, and outputs the results using the board LEDs.

Figure 1. MIPI CSI-2 TX Controller Core Example Design
After power-up and device programming is done, the following response can be observed:
  • LED0_B—Blinks continuously indicating there are traffic being sent over to MIPI IP.
  • LED0_G—Turns on to indicate that the hsync signal matches TX and RX.
  • LED1_B—Turns on to indicate that the vsync signal matches TX and RX.
  • LED1_G—Turns on to indicate that the pixel data signal matches TX and RX.
  • LED1_R—turns on to indicate that the pixel data valid signal matches TX and RX.

The RX clock to RX data skew varies in different board, hence there is a possibility where the RX clock might not be able to capture the RX data correctly. In this case, both the LEDs do not turn on. You have to try increase the Static Mode Delay Setting of mipi_dphy_rx_data in the Interface Designer.

Note: You can use the Titanium MIPI Utility-v<version>.xlsm to check if your own design will work. Enter the related design information then verify whether your selections pass various tests. You can download the Titanium MIPI utility from the Design Support page in the Support Center.

Table 1. Example Design Implementation
FPGA Logic Elements (Logic, Adders, Flipflops, etc.) Memory Blocks DSP Blocks fMAX (MHz)1 Efinity® Version2
clk1 clk2 clk3 clk4
Ti60 F225 C4 6,329/60,800 (10.4%) 44/256 (17.2%) 0/160 (0%) 231 298 233 265 2024.2.294.4.12
  • clk1—mipi_clk
  • clk2—mipi_dphy_rx_clk_CLKOUT
  • clk3—clk_pixel
  • clk4—mipi_dphy_tx_SLOWCLK
1 Using default parameter settings.
2 Using Verilog HDL.