Ports

Table 1. Clock and Reset Ports
Port	Direction	Description
clk	Input	IP core clock consumed by controller logics. 100 MHz.
reset_n	Input	IP core reset signal.
clk_byte_HS	Input	MIPI TX parallel clock. This is a HS mode transmission clock.
reset_byte_HS_n	Input	MIPI TX parallel clock reset signal.
clk_pixel	Input	Pixel clock.
reset_pixel_n	Input	Pixel clock reset signal.
axi_clk	Input	AXI4-Lite interface clock.
axi_reset_n	Input	AXI4-Lite interface reset.

Note: Refer to the Interfaces User Guide in the Support Center for serial or parallel clock requirements.

Table 2. MIPI TX I/O interface
Port	Direction	Description
Tx_LP_CLK_P	Output	LP mode TX clock single-ended P signal.
Tx_LP_CLK_N	Output	LP mode TX clock single-ended N signal.
Tx_LP_CLK_P_OE	Output	Output enable for LP mode TX clock single-ended P signal.
Tx_LP_CLK_N_OE	Output	Output enable for LP mode TX clock single-ended N signal.
Tx_HS_enable_C	Output	Signal to enable HS mode clock lane.
Tx_LP_D_P [NUM_DATA_LANE-1:0]	Output	LP mode TX data single-ended P signal.
Tx_LP_D_N [NUM_DATA_LANE-1:0]	Output	LP mode TX data single-ended N signal.
Tx_LP_D_P_OE [NUM_DATA_LANE-1:0]	Output	Output enable for LP mode TX data single-ended P signal.
Tx_LP_D_N_OE [NUM_DATA_LANE-1:0]	Output	Output enable for LP mode TX data single-ended N signal.
Tx_HS_D_n[7:0]	Output	HS mode differential lane data bus. n = lane 0 to 7
Tx_HS_enable_D [NUM_DATA_LANE-1:0]	Output	Signal to enable HS mode data lane.
Tx_HS_C [7:0]	Output	HS mode differential clock bus.

Table 3. Video InterfaceAll signals are clocked with clk_pixel and reset_pixel_n.
Port	Direction	Description
hsync_vcx	Input	Active-high horizontal sync for virtual channel. x = virtual lane 0 to 15
vsync_vcx	Input	Active-high vertical sync for virtual channel. x = virtual lane 0 to 15
datatype [5:0]	Input	Data type of the long packet. Sampled at Hsync rising edge.
pixel_data [63:0]	Input	Video Data. The actual width is dependent on pixel type. Refer to the pixel encoding table.
pixel_data_valid	Input	Active-high pixel data enable. Once the TX VALID signal goes high, the MIPI TX interface expects to receive pixel data every clock cycle until the entire line is sent. Additionally, the TX VALID signal must remain high for the entire line.
haddr [15:0]	Input	16 bit horizontal number of pixels. Sampled at Hsync rising edge. Note: Total pixel count should be aligned to pixels-per-clock boundary to prevent ambiguity on the pixel_data[63:0].
line_num[15:0]	Input	Line number to use. Sampled at Hsync rising edge.
frame_num[15:0]	Input	Frame number to use. Sampled at Vsync rising edge.

Table 4. AXI4-Lite Interface
Interface to access Table 1.

All signals are clocked with axi_clk and axi_reset_n.
Port	Direction	Description
axi_awaddr [15:0]	Input	AXI4-Lite write address bus.
axi_awvalid	Input	AXI4-Lite write address valid strobe.
axi_awready	Output	AXI4-Lite write address ready signal.
axi_wdata [31:0]	Input	AXI4-Lite write data.
axi_wvalid	Input	AXI4-Lite write data valid strobe.
axi_wready	Output	AXI4-Lite write ready signal.
axi_bvalid	Output	AXI4-Lite write response valid strobe.
axi_bready	Input	AXI4-Lite write response ready signal.
axi_araddr [15:0]	Input	AXI4-Lite read address bus.
axi_arvalid	Input	AXI4-Lite read address valid strobe.
axi_arready	Output	AXI4-Lite read address ready signal.
axi_rdata [31:0]	Output	AXI4-Lite read data.
axi_rvalid	Output	AXI4-Lite read data valid strobe.
axi_rready	Input	AXI4-Lite read data ready signal.

Table 5. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.
Port	Direction	Description
mipi_debug_out[31:0]	Output	Debug port. Present if the parameter MIPI_CSI2_TX_DEBUG is Enabled. The following is the list of internal signals that can be monitored. [0] = fifo_full [1] = fifo_empty [2] = non_support_longpkt [3] = ready_to_xmit (indicator for initialization done, prior to skewcal) [4] = init_skewcal_done (indicator for skewcal process completion) [5] = TxStopState_0 [6] = TxStopState_1 [7] = TxStopState_2 [8] = TxStopState_3 [9] = TxStopState_4 [10] = TxStopState_5 [11] = TxStopState_6 [12] = TxStopState_7 [31:13] = reserved
mipi_debug_in[31:0]	Input	Debug ports. Present if the parameter MIPI_CSI2_TX_DEBUG is Enabled. Currently no function has been implemented. Tie all input bits to zero. [31:0] = reserved