Tz325 Programmable Duty Cycle

Tz325 FPGAs support a programmable duty cycle on the CLKOUT1 signal. A programmable duty cycle means that the clock's highs and lows can be different lengths (see Figure 1).

If you turn on output clock inversion, the duty cycle setting is applied before the clock is inverted.

Figure 1. Programmable Duty Cycle Example

Important: You cannot use the programmable duty cycle at the same time as the fractional output divider.