Tz325 Revision History

Table 1. Revision History
Date Version Description
February 2026 1.4 Updated DSP block diagram; W register moved to after adder. (DOC-2592)
Updated Table 2.
Updated Table 6. (DOC-2803)
Note added regarding reconfiguration to Tz325 Internal Reconfiguration Block.
Corrected definition for MIPI D-PHY signal ERR_SOT_HS_LANn; SOT is start of transmission. (DOC-2755)
The Efinity software issues a warning (not error) if you do not leave enough separation between GPIO and LVDS or MIPI lane pins (see note). (DOC-2833)
Corrected number of MIPI D-PHY hard blocks for N900 package in Table 2. (DOC-2811)
Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)
Added transceiver analog power supply (VDDA_H_Q) specification. (DOC-2910)
Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)
October 2025 1.3 Added notes for Tz325 Single-Event Upset Detection. (DOC-2602)
Reduced minimum PMA Direct data rate. (DOC-2601)
Added note referring customer to AN 063 for PMA Direct Rx insertion loss guidelines. (DOC-2655)
Updated Figure 4; some N signals were incorrectly labeled as P. (DOC-2676)
July 2025 1.2
Added Tz325 Transceiver Specifications topic. (DOC-2282)
Updated PLL maximum locked time Table 2 (DOC-2468)
Corrected link to Topaz DDR DRAM Block User Guide. (DOC-2300)
Updated configuration timing and fuse programming waveforms. (DOC-2272)
Moved table describing connection requirements for unused resources and features to the Tz325 Unused Resources and Features topic.
Updated differential I/O programmable delay chain step size specification. (DOC-2351)
Updated regional clock network figures to show that GPIOB_PN_01, GPIOB_PN_05, and GPIOB_PN_12 are MIPI RX clocks. (DOC-2389)
Corrected resource names in PLL reference clock resource assignments tables.
In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)
Added RISC-V memory clock speed to Table 19. (DOC-2278)
November 2024 1.1
Added DLYCLK GPIO signal. (DOC-2159)
Updated GPIO and LVDS interface pin names (IN to I and OUT to O) to align with primitives. (DOC-2086)
Removed PLL IOFBK interface pin.
The SAMPLE/PRELOAD instruction is available after JTAG fuses have been blown. (DOC-2225)
Fixed typo in Table 2. (DOC-2038)
Changed column name from Pins to Configuration Functions in Table 2. (DOC-2038)
Added note after Table 2 directing the reader to the device pinout file. (DOC-2038)
Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)
Clarified HVIO and HSIO pin states during configuration and when unused in user mode. (DOC-2041)
Added notes to the configuration timing and security feature topics about not using SPI and JTAG at the same time. (DOC-2047)
The transceiver supplies can be powered up in any sequence. (DOC-2131)
Updated configuration timing and fuse programming waveforns. (DOC-2156)
October 2024
 1.0 Initial release.