Efinix, Inc.
  • Tz325 Introduction
  • Tz325 Features
    • Tz325 Available Package Options
  • Tz325 Device Core Functional Description
    • Tz325 XLR Cell
    • Tz325 Embedded Memory
      • Tz325 True Dual-Port Mode
      • Tz325 Simple Dual-Port Mode
    • Tz325 DSP Block
    • Tz325 Clock and Control Network
      • Tz325 Clock Sources that Drive the Global and Regional Networks
      • Tz325 Driving the Global Network
      • Tz325 Driving the Regional Network
      • Tz325 Driving the Local Network
  • Tz325 Device Interface Functional Description
    • Tz325 Interface Block Connectivity
    • Tz325 GPIO
      • Tz325 Features for HVIO and HSIO Configured as GPIO
        • Tz325 Double-Data I/O
        • Tz325 Programmable Delay Chains
      • Tz325 HVIO
      • Tz325 HSIO
        • Tz325 HSIO Configured as GPIO
        • Tz325 HSIO Configured as LVDS
        • Tz325 HSIO Configured as MIPI Lane
      • I/O Banks
    • Tz325 DDR DRAM Interface
    • Tz325 MIPI D-PHY
      • Tz325 MIPI RX D-PHY
      • Tz325 MIPI TX D-PHY
    • Tz325 Oscillator
    • Tz325 Fractional PLL
      • Tz325 Reference Clock Resource Assignments
      • Tz325 Programmable Duty Cycle
      • Tz325 Fractional Output Divider
      • Tz325 Spread-Spectrum Clocking
      • Tz325 Dynamic PLL Reconfiguration
      • Tz325 Dynamic Phase Shift
    • Tz325 Spread-Spectrum Clocking PLL
    • Tz325 Hardened RISC-V Block Interface
    • Tz325 Transceiver Interface
    • Tz325 Single-Event Upset Detection
    • Tz325 Internal Reconfiguration Block
  • Tz325 Security Feature
  • Tz325 Power Sequence
    • Tz325 Power-Up Sequence
    • Tz325 Power-Down Sequence
    • Tz325 Power Supply Current Transient
    • Tz325 Unused Resources and Features
  • Tz325 Configuration
    • Tz325 Supported Configuration Modes
  • Tz325 Characteristics and Timing
    • Tz325 DC and Switching Characteristics
    • Tz325 HSIO Electrical and Timing Specifications
    • Tz325 MIPI Electrical Specifications and Timing
      • Tz325 MIPI Reset Timing
    • Tz325 PLL Timing and AC Characteristics
    • Tz325 Configuration Timing
      • Tz325 JTAG Mode
      • Tz325 SPI Active Mode
      • Tz325 SPI Passive Mode
    • Tz325 Transceiver Specifications
  • Tz325 Pinout Description
    • Tz325 Configuration Pins
    • Tz325 Dedicated DDR Pinout
    • Tz325 Dedicated MIPI D-PHY Pinout
    • Tz325 Dedicated Transceiver Pinout
    • Tz325 Pin States
  • Tz325 Interface Floorplan
  • Tz325 Efinity Software Support
  • Tz325 Ordering Codes
  • Tz325 Revision History

Tz325 Internal Reconfiguration Block

The Tz325 FPGAs have built-in hardware that supports an internal reconfiguration feature. The Tz325 can reconfigure itself from a bitstream image stored in flash memory.

Note: Refer to AN 010: Using the Internal Reconfiguration Feature to Update Efinix FPGAs Remotely for details regarding reconfiguration.
Parent topic: Tz325 Device Interface Functional Description

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