Efinix, Inc.
  • Tz170 Introduction
  • Tz170 Features
    • Tz170 Package-Dependent Resources
    • Tz170 Available Package Options
  • Tz170 Device Core Functional Description
    • Tz170 XLR Cell
    • Tz170 Embedded Memory
      • Tz170 True Dual-Port Mode
      • Tz170 Simple Dual-Port Mode
    • Tz170 DSP Block
    • Tz170 Clock and Control Network
      • Tz170 Clock Sources that Drive the Global and Regional Networks
      • Tz170 Driving the Global Network
      • Tz170 Driving the Regional Network
      • Tz170 Driving the Local Network
  • Tz170 Device Interface Functional Description
    • Tz170 Interface Block Connectivity
    • Tz170 GPIO
      • Tz170 Features for HVIO and HSIO Configured as GPIO
        • Tz170 Double-Data I/O
        • Tz170 Programmable Delay Chains
      • Tz170 HVIO
      • Tz170 HSIO
        • Tz170 HSIO Configured as GPIO
        • Tz170 HSIO Configured as LVDS
        • Tz170 HSIO Configured as MIPI Lane
      • ITz170 /O Banks
    • Tz170 DDR DRAM Interface
    • Tz170 MIPI D-PHY
      • Tz170 MIPI RX D-PHY
      • Tz170 MIPI TX D-PHY
    • Tz170 Oscillator
    • Tz170 PLL
      • Tz170 Dynamic Phase Shift
    • Tz170 Spread-Spectrum Clocking PLL
    • Tz170 Single-Event Upset Detection
    • Tz170 Internal Reconfiguration Block
  • Tz170 Security Feature
  • Tz170 Power Sequence
    • Tz170 Power-Up Sequence
    • Tz170 Power-Down Sequence
    • Tz170 Power Supply Current Transient
    • Tz170 Unused Resources and Features
  • Tz170 Configuration
    • Tz170 Supported Configuration Modes
  • Tz170 Characteristics and Timing
    • Tz170 DC and Switching Characteristics
    • Tz170 HSIO Electrical and Timing Specifications
    • Tz170 MIPI Electrical Specifications and Timing
      • Tz170 MIPI Reset Timing
    • Tz170 PLL Timing and AC Characteristics
    • Tz170 Configuration Timing
      • Tz170 JTAG Mode
      • Tz170 SPI Active Mode
      • Tz170 SPI Passive Mode
  • Tz170 Pinout Description
    • Tz170 Configuration Pins
    • Tz170 Dedicated DDR Pinout
    • Tz170 Dedicated MIPI D-PHY Pinout
    • Tz170 Pin States
  • Tz170 Interface Floorplan
  • Tz170 Efinity Software Support
  • Tz170 Ordering Codes
  • Tz170 Revision History

Tz170 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Topaz FPGAs.
  • Tz170 Power-Up Sequence
  • Tz170 Power-Down Sequence
  • Tz170 Power Supply Current Transient
  • Tz170 Unused Resources and Features

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