Efinix, Inc.
  • Tz110 Introduction
  • Tz110 Features
    • Tz110 Package-Dependent Resources
    • Tz110 Available Package Options
  • Tz110 Device Core Functional Description
    • Tz110 XLR Cell
    • Tz110 Embedded Memory
      • Tz110 True Dual-Port Mode
      • Tz110 Simple Dual-Port Mode
    • Tz110 DSP Block
    • Tz110 Clock and Control Network
      • Tz110 Clock Sources that Drive the Global and Regional Networks
      • Tz110 Driving the Global Network
      • Tz110 Driving the Regional Network
      • Tz110 Driving the Local Network
  • Tz110 Device Interface Functional Description
    • Tz110 Interface Block Connectivity
    • Tz110 GPIO
      • Tz110 Features for HVIO and HSIO Configured as GPIO
        • Tz110 Double-Data I/O
        • Tz110 Programmable Delay Chains
      • Tz110 HVIO
      • Tz110 HSIO
        • Tz110 HSIO Configured as GPIO
        • Tz110 HSIO Configured as LVDS
        • Tz110 HSIO Configured as MIPI Lane
      • ITz110 /O Banks
    • Tz110 DDR DRAM Interface
    • Tz110 MIPI D-PHY
      • Tz110 MIPI RX D-PHY
      • Tz110 MIPI TX D-PHY
    • Tz110 Oscillator
    • Tz110 PLL
      • Tz110 Dynamic Phase Shift
    • Tz110 Spread-Spectrum Clocking PLL
    • Tz110 Single-Event Upset Detection
    • Tz110 Internal Reconfiguration Block
  • Tz110 Security Feature
  • Tz110 Power Sequence
    • Tz110 Power-Up Sequence
    • Tz110 Power-Down Sequence
    • Tz110 Power Supply Current Transient
    • Tz110 Unused Resources and Features
  • Tz110 Configuration
    • Tz110 Supported Configuration Modes
  • Tz110 Characteristics and Timing
    • Tz110 DC and Switching Characteristics
    • Tz110 HSIO Electrical and Timing Specifications
    • Tz110 MIPI Electrical Specifications and Timing
      • Tz110 MIPI Reset Timing
    • Tz110 PLL Timing and AC Characteristics
    • Tz110 Configuration Timing
      • Tz110 JTAG Mode
      • Tz110 SPI Active Mode
      • Tz110 SPI Passive Mode
  • Tz110 Pinout Description
    • Tz110 Configuration Pins
    • Tz110 Dedicated DDR Pinout
    • Tz110 Dedicated MIPI D-PHY Pinout
    • Tz110 Pin States
  • Tz110 Interface Floorplan
  • Tz110 Efinity Software Support
  • Tz110 Ordering Codes
  • Tz110 Revision History

Tz110 Internal Reconfiguration Block

The Tz110 FPGAs have built-in hardware that supports an internal reconfiguration feature. The Tz110 can reconfigure itself from a bitstream image stored in flash memory.

Note: Refer to AN 010: Using the Internal Reconfiguration Feature to Update Efinix FPGAs Remotely for details regarding reconfiguration.
Parent topic: Tz110 Device Interface Functional Description

Copyright (c) 2026 | All Rights Reserved