Tz110 DSP Block
The Topaz FPGA has high-performance, complex DSP blocks that can perform multiplication, addition, subtraction, accumulation, and 4-bit variable right shifting. The 4-bit variable right shift supports one lane in normal mode, two lanes in dual mode and four lanes in quad mode. Each DSP block has four modes, which support the following multiplication operations:
- Normal—One 19 × 18 integer multiplication with 48-bit addition/subtraction.
- Dual—One 11 × 10 integer multiplication and one 8 × 8 integer multiplication with two 24-bit additions/subtractions.
- Quad—One 7 × 6 integer multiplication and three 4 × 4 integer
multiplications with four 12-bit additions/subtractions.Important: The 7 × 6 Quad mode output is truncated to 12-bit.
- Float—One fused-multiply-add/subtract/accumulate (FMA) BFLOAT16 multiplication.
The integer multipliers can represent signed or unsigned values based on the
SIGNED parameter. When multiple EFX_DSP12 or EFX_DSP24 primitives
are mapped to the same DSP block, they must have the same SIGNED value.
The inputs to the multiplier are the A and B data inputs. Optionally, you can use the
result of the multiplier in an addition or subtraction operation.
