Tz110 Revision History

Updated DSP block diagram; W register moved to after adder. (DOC-2592)

Updated Table 2.

Corrected definition for MIPI D-PHY signal ERR_SOT_HS_LANn; SOT is start of transmission. (DOC-2755)

Updated the presentation of the LPDDR4/4x resource information in Table 1 to be consistent with other data sheets. (DOC-2814)

The Efinity software issues a warning (not error) if you do not leave enough separation between GPIO and LVDS or MIPI lane pins (see note). (DOC-2833)

Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)

Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)

Updated Figure 1 and Figure 4; some N signals were incorrectly labeled as P. (DOC-2676)

Updated Table 4; updated signal direction.

Updated AWCOBUF_x in Table 10.

Updated NSTATUS description in Table 2.

Updated NSTATUS pin state during reset and configuration in Table 1. (DOC-2727)

Corrected link to Topaz DDR DRAM Block User Guide. (DOC-2300)

Updated configuration timing and fuse programming waveforms. (DOC-2272)

Moved table describing connection requirements for unused resources and features to the Tz110 Unused Resources and Features topic.

In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)

Added DLYCLK GPIO signal. (DOC-2159)

Updated GPIO and LVDS interface pin names (IN to I and OUT to O) to align with primitives. (DOC-2086)

Removed PLL IOFBK interface pin.

The SAMPLE/PRELOAD instruction is available after JTAG fuses have been blown. (DOC-2225)