Ti60 I/O Banks

Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has independent power pins. The number and voltages supported vary by FPGA and package.

Some I/O banks are merged at the package level by sharing VCCIO pins, these are called merged banks. Merged banks have underscores (_) between banks in the VCCIO name (e.g., 1B_1C means VCCIO for bank 1B and 1C are connected). Some of the banks in a merged bank may not have available user I/Os in the package. The following table lists banks that have available user I/Os in a package.

Table 1. I/O Banks by Package

Package	I/O Banks	Voltage (V)	Dynamic Voltage Support	DDIO Support	Merged Banks
W64, V64	1A, 1B, 3B	1.2, 1.35, 1.5, 1.8	–	All	1A_4B, 1B_2A, 2B_3A_3B_4A
F100	1A, 2A	1.2, 1.35, 1.5, 1.8	–	All	1A_4B, 2A_2B
	1B, 3A, 3B	1.2, 1.35, 1.5, 1.8	–	All	3B_4A
	BL	1.8, 2.5, 3.0, 3.3		All	–
F100S3F2	1A, 2A	1.2, 1.35, 1.5, 1.81	–	All	1A_4B, 2A_2B
	1B, 3A, 3B	1.2, 1.35, 1.5, 1.8	–	All	3B_4A
	BL	1.8, 2.5, 3.0, 3.3		All	–
F225 F256	BL, TL, TR, BR,	1.8, 2.5, 3.0, 3.3		All	–
	1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B	1.2, 1.35, 1.5, 1.8	–	All	–