Efinix, Inc.
  • Ti60 Introduction
  • Ti60 Features
    • Ti60 Available Package Options
  • Ti60 Device Core Functional Description
    • Ti60 XLR Cell
    • Ti60 Embedded Memory
      • Ti60 True Dual-Port Mode
      • Ti60 Simple Dual-Port Mode
    • Ti60 DSP Block
    • Ti60 Clock and Control Network
      • Ti60 Clock Sources that Drive the Global and Regional Networks
      • Ti60 Driving the Global Network
      • Ti60 Driving the Regional Network
      • Ti60 Driving the Local Network
  • Ti60 Device Interface Functional Description
    • Ti60 Interface Block Connectivity
    • Ti60 GPIO
      • Ti60 Features for HVIO and HSIO Configured as GPIO
        • Ti60 Double-Data I/O
        • Ti60 Programmable Delay Chains
      • Ti60 HVIO
      • Ti60 HSIO
        • Ti60 HSIO Configured as GPIO
        • Ti60 HSIO Configured as LVDS
        • Ti60 HSIO Configured as MIPI Lane
      • Ti60 I/O Banks
    • Ti60 Oscillator
    • Ti60 PLL
      • Ti60 Dynamic Phase Shift
    • Ti60 SPI Flash Memory
    • Ti60 HyperRAM Interface
    • Ti60 Single-Event Upset Detection
    • Ti60 Internal Reconfiguration Block
  • Ti60 Security Feature
  • Ti60 Power Sequence
    • Ti60 Power-Up Sequence (No VQPS)
    • Ti60 Power-Up Sequence (VQPS)
    • Ti60 Power-Down Sequence
    • Ti60 Power Supply Current Transient
    • Ti60 Unused Resources and Features
  • Ti60 Configuration
    • Ti60 Supported FPGA Configuration Modes
  • Ti60 Characteristics and Timing
    • Ti60 DC and Switching Characteristics
    • Ti60 HSIO Electrical and Timing Specifications
    • Ti60 PLL Timing and AC Characteristics
    • Ti60 HyperRAM Characteristics
    • Ti60 Configuration Timing
      • Ti60 JTAG Mode
      • Ti60 SPI Active Mode
      • Ti60 SPI Passive Mode
  • Ti60 Pinout Description
    • Ti60 Configuration Pins
    • Ti60 Pin States
  • Ti60 Interface Floorplan
  • Ti60 Efinity Software Support
  • Ti60 Ordering Codes
  • Ti60 Revision History

Ti60 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Titanium FPGAs.
  • Ti60 Power-Up Sequence (No VQPS)
  • Ti60 Power-Up Sequence (VQPS)
  • Ti60 Power-Down Sequence
  • Ti60 Power Supply Current Transient
  • Ti60 Unused Resources and Features

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