Ti60 Power-Up Sequence (VQPS)

Important: This sequence applies to Ti60 FPGAs in V64, F100, and F256 packages (all lots), as well as F100S3F2 and F225 packages with the letter S in the lot number. For F100S3F2 and F225 packages that do not have the letter S in the lot number, refer to Ti60 Power-Up Sequence (No VQPS). See PCN-2405-001 for details.
Figure 1. Power-Up Sequence

Important: You can only use one configuration channel at a time. Using SPI passive and JTAG at the same time can result in configuration failure.
  1. The CRESET_N input must stay low until all power supplies are powered up. Additionally, VQPS must always stay low unless you are blowing the Ti60 security fuses.
    Note: Refer to Fuse Programming Requirements if you need to blow the security fuses for the Ti60 FPGA on your board.
  2. Power up VCC and VCCA_xx first. You can power up these supplies in any sequence.
    Important: Ensure the power ramp rate is within the values shown in Table 3.
  3. Power up all VCCIO and VCCAUX in any sequence at a minimum delay of 10 µs after the VCC and VCCA_xx supplies have reached 90% of their nominal voltage levels.
  4. Release the CRESET_N input to high at a minimum delay of 10 µs after all supplies have reached 90% of their nominal voltage levels.
    Note: With the configuration bitstream stored in the SPI flash device and the SPI active hardware connection properly established, the SPI active configuration automatically starts after the CRESET_N signal transitions from low to high.