Ti60 Embedded Memory

The core has 10-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM. You can initialize the memory content during configuration. The Efinity® software includes a memory cascading feature to connect multiple blocks automatically to form a larger array. This feature enables you to instantiate deeper or wider memory modules.

Note: The block RAM content is random and undefined if it is not initialized.

The read and write ports support independently configured data widths, an address enable, and an output register reset. The simple dual-port mode also supports a write byte enable.

Notice: Refer to the Quantum® Titanium Primitives User Guide for details on the Titanium™ RAM configuration.

Ti60 True Dual-Port Mode

The memory read and write ports have the following modes for addressing the memory (depth × width):

1024 × 8 2048 × 4 4096 × 2
8192 × 1 1024 × 10 2048 × 5
Figure 1. RAM Block Diagram (True Dual-Port Mode)

Ti60 Simple Dual-Port Mode

The memory read and write ports have the following modes for addressing the memory (depth × width):

512 × 16 1024 × 8 2048 × 4 4096 × 2
8192 × 1 512 × 20 1024 × 10 2048 × 5
Figure 2. Simple Dual-Port Mode RAM Block Diagram (512 × 20 Configuration)