Ti120 Revision History

Updated DSP block diagram; W register moved to after adder. (DOC-2592)

Updated Table 2.

Corrected definition for MIPI D-PHY signal ERR_SOT_HS_LANn; SOT is start of transmission. (DOC-2755)

Updated the presentation of the LPDDR4/4x resource information in Table 1 to be consistent with other data sheets. (DOC-2814)

The Efinity software issues a warning (not error) if you do not leave enough separation between GPIO and LVDS or MIPI lane pins (see note). (DOC-2833)

Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)

Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)

Updated Figure 1 and Figure 4; some N signals were incorrectly labeled as P. (DOC-2676)

Updated Table 4; updated signal direction.

Updated AWCOBUF_x in Table 10.

Updated NSTATUS description in Table 2.

Updated NSTATUS pin state during reset and configuration in Table 1. (DOC-2727)

Updated configuration timing and fuse programming waveforms. (DOC-2272)

Moved table describing connection requirements for unused resources and features to the Ti120 Unused Resources and Features topic.

In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)

Added DLYCLK GPIO signal. (DOC-2159)

Updated GPIO and LVDS interface pin names (IN to I and OUT to O) to align with primitives. (DOC-2086)

Removed PLL IOFBK interface pin.

The SAMPLE/PRELOAD instruction is available after JTAG fuses have been blown. (DOC-2225)

Updated configuration timing and fuse programming waveforns. (DOC-2156)

Clarified HVIO and HSIO pin states during configuration and when unused in user mode. (DOC-2041)

Corrected MIPI D-PHY interface performance specification. (DOC-2064)

Fixed typo in Table 2. (DOC-2038)

Changed column name from Pins to Configuration Functions in Table 2. (DOC-2038)

Added note after Table 2 directing the reader to the device pinout file. (DOC-2038)

Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)

Removed duplicate specification for F_OUT in PLL Timing and AC Characteristics topic. (DOC-1947)

Clarified which signals are available when LVDS settings are enabled. (DOC-1908)

Added reset recommendations for PLLs and cascaded PLLs. (DOC-1900)

Removed duplicate paragraph about the XLR cell.

Updated LPDDR4/4x and MIPI D-PHY performance specifications for Q3 speed grade.

Added automotive speed grade to features.

Added Q3 (automotive) specifications.

Added EXTFB to table of alternate pin functions.

Added LPDDR4 DRAM controller power pins to the Absolute Maximum Ratings table.

Combined tables of Recommended Operating Conditions into one for ease of use.

Added pipeline mode for DDIO. (DOC-1571)

Updated power ramp-up details in Ti120 Power-Up Sequence. (DOC-1683)

Added note to Ti120 Power-Up Sequence about DDR DRAM power supply requirements. (DOC-1573)

Removed t_{MIPI_Power} (MIPI power-up details provided in Ti120 Power-Up Sequence). (DOC-1609)

Updated Power-Up Groups table.

Moved dedicated DDR and MIPI D-PHY pinouts into separate sections.

Corrected OUTCLK connection in Figure 1. (DOC-1630)

Rearranged Ti120 Configuration Timing to keep waveforms together with tables.

Updated the configuration timing waveforms for SPI active and SPI passive.

For the PLL equation F_VCO = (F_PFD x M x O x C_FBK ), removed the restriction that (M x O x C_FBK) must be ≤ 255.

Corrected block RAM count. (DOC-1685)

Removed M361, M484, and F529 packages. (DOC-1731)

MIPI D-PHY specification is v1.1. (DOC-1610)

Updated MIPI RCLKs in image of Clock Sources that Drive the Regional Network. (DOC-1362)

Removed table Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic. Added 3.3 V and 2.5 V in table HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics. Added table Supported HVIO Drive Strength and Supported HSIO Drive Strength. (DOC-1377)

Updated min ramp time in table Power Supply Ramp Rates. (DOC-1407)

Updated MIPI D-PHY in table title and pinout description in table Dedicated MIPI D-PHY Pinouts. Previously table was MIPI Pinout (Dedicated). (DOC-1409)

Updated input leakage limit in table HVIO DC Electrical Characteristics, and HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics. (DOC-1411)

Added important note to highlight the CRESET_N requirement during power-up sequence. (DOC-1443)

Updated image Power-Up Sequence. Removed VQPS from Group 2 in table Power-Up Groups by Package Variation and combined Group 2 and 3 together. Changed to GND from 1.8 V for Security (Fuse Blowing) in table Connection Requirements for Unused Resources and Features. Added section Fuse Programming Requirements in Security Features. (DOC-1467)

Corrected typo for VCCIO33 max supply in Absolute Maximum Ratings table. (DOC-1483)

Added max. value of f_TCK at 3 MHz at an operating voltage of 1.8 V to in JTAG Mode table. Added max. value of V_IL at 0.28 V for 1.8 V JTAG Configuration in HVIO DC Electrical Characteristics. (DOC-1510)

Corrected typo in HSIO Pins Configured as Differential SSTL I/O Electrical Characteristics table. (DOC-1514)

Added Power-Down Sequence topic.

Updated value of power supply current transient to 1500 mA in table Minimum Power Supply Current Transient.

Updated initial CCK waveform of figure SPI Passive Mode (x1) Timing Sequence.

Updated Programmable Delay Chains section, and added static and dynamic delay step size specs. (DOC-1342)

Added G400 package. (DOC-1384)

Added note about keeping both the current and the next clocks toggling during dynamic clock switching. (DOC-1405)

Added note about 7 x 6 Quad mode output is truncated to 12-bit (DOC-1295)

Added slvs option for HSIO configured as LVDS blocks. (DOC-1190)

Added Spread-Spectrum Clocking PLL block. (DOC-1178)

Updated DDR_DM signal description. (DOC-1322)

Updated 2.5 V LVCMOS max toggle rate. (DOC-1251)

Updated LPDDR4 interface maximum data rate for J361, J484, and G529 packages. (DOC-1249)

Replaced t_{LVDS_DT} and t_INDT specs with t_{PLL_HLW} and t_{LVDS_CPA}. (DOC-1189)

Updated PLL LOCKED signal description. (DOC-1208)

Added LVDS RX DBG signals. (DOC-1124)

Added note about using LVDS blocks from the same side of the FPGA to minimize skew. (DOC-1150)

Updated DDR DRAM interface input clock to include description for J361, J484, and G529 packages. (DOC-1209)

Updated PLL RSTN signal description about de-asserting only when CLKIN is stable. (DOC-1226)

Corrected PLL_SSC_EN MIPI TX D-PHY signal notes. (DOC-1101)

Corrected VDDQ_CK_PHY pin name and standardized VCCA pin names. (DOC_1114)

Added note about achieving maximum toggle rate. (DOC-1099)

Added link in Power Up Sequence pointing to the Web Interactive Hardware Design Checklist and Guidelines. (DOC-1123)

Updated REF_RES_3A pin connection requirement in the Pinout Description topic.

Updated VQPS power-down sequence note.

Added connection requirement when unused for VQPS.

Added VQPS in power up sequence requirement. (DOC-951)

Updated M361, M484, and F529 LPDDR4/4x to only support x16 DQ width.

Added floorplan diagrams. (DOC-1016)

Updated Clock Sources that Drive the Regional Network diagram. (DOC-969)

Updated configuration pins external weak pull-up requirements. (DOC-1035)

Updated DDR signal name from ARST_x to ARSTN_x. (DOC-1025)

Added DPA specs and updated DPA description to support full-rate serialization mode only. (DOC-1078)

Updated LVDS and sub-LVDS specs to include half-rate and full-rate serialization. (DOC-1078)

Updated JTAG configuration timing specs. (DOC-1083)

Updated REF_RES_xx pins connection requirement. (DOC-943)

Removed GCTRL and RCTRL. (DOC-895)

Corrected AWID_x, AWREADY_x, ARADDR_x, and AWADDR_x DDR signals directions and widths. (DOC-907)

Updated DDR DRAM Performance specs. (DOC-900)

Added note recommending up to only 2 cascading PLLs. (DOC-931)

Updated description about differential receivers are powered by VCCAUX. (DOC-929)

Updated t_{CRESET_N} spec. (DOC-876)

Updated DDR DRAM block CLKIN resource. (DOC-881)

Corrected MIPI RX Lane Block Diagram. (DOC-878)

Added MIPI D-PHY maximum data rate specs.

Removed footnote in Minimum Power Supply Current Transient table. (DOC-818)

Updated MIPI D-PHY port names. (DOC-782)

Updated DDR power supplies to match pinout and Efinity software. (DOC-795)

Added L484 package specs and features. (DOC-821)

Updated and improved clock and control network content and figures. (DOC-668)

Updated the power up sequence topics.

Updated package-dependent resources table.

Added I4 and I4L packages.

Updated DDR and MIPI DPHY block pad names.

Removed SPI and JTAG Pins in Secure Mode topic.

Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781)

Corrected description for differential TX static programmable delay. (DOC-786)

Added PLL period jitter spec with noisy input clock specs and updated test condition note. (DOC-771)

Updated figure title for Connections for Clock and RX Data Lane in the Same MIPI RX Group. (DOC-739)

Updated LVDS/RSDS/mini-LVDS RX supported VCCIO. (DOC-740)

Added Power Supply Current Transient. (DOC-761)

Corrected RD and RST signal directions in MIPI RX Lane Block Diagram.

Updated power supply ramp rate and power up sequence diagram. (DOC-631)

Updated external pull-up requirement for dual-purpose configuration pins. (DOC-734)

Updated active and passive configuration timing specs. (DOC-708)

Updated 2.5 V LVCMOS V_IH and V_IL specs. (DOC-718)

Added I_IN and V_IN specs. (DOC-652)

Updated MIPI and LVDS maximum toggle rate.

Updated available package options.

Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729)

Added MIPI and DDR pins in pinout description. (DOC-712)

Updated M361 package available resources.

Added Schmitt Trigger input buffer specs. (DOC-606)

Added PLL reference clock input duty cycle specs. (DOC-661)

Updated HVIO maximum toggle rate specs. (DOC-689)

Removed I4 and I4L speed grades. (DOC-681)

Updated global clock buffer, DSP, BRAM, HSIO as LVDS, and HSIO as MIPI lane specs. (DOC-693)

Added internal weak pull-up resistor and drive strength specs for CDONE and CRESET_N. (DOC-635)

Added ambient storage temperature spec. (DOC-678)