Ti120 Power-Up Sequence

Important: You can only use one configuration channel at a time. Using SPI passive and JTAG at the same time can result in configuration failure.

The CRESET_N input must stay low until all power supplies are powered up. Additionally, VQPS must always stay low unless you are blowing the Ti120 security fuses.
Note: Refer to Fuse Programming Requirements if you need to blow the security fuses for the Ti120 FPGA on your board.
Power up supplies in group 1 first. You can power up these supplies in any sequence.
Important: Ensure the power ramp rate is within the values shown in Table 3.
Power up the group 2 supplies in any sequence at a minimum delay of 10 µs after group 1 supplies have reached 90% of their nominal voltage levels.
Release the CRESET_N input to high at a minimum delay of 10 µs after all FPGA supplies have reached 90% of their nominal voltage levels.
FPGA configuration can begin after there has been:
- A 4.5 ms minimum delay after all supplies have reached at least 90% of their nominal voltage.
- A t_DMIN minimum delay after CRESET_N goes high (see Ti120 SPI Passive Mode and Ti120 JTAG Mode for the delay specification).
Note: With the configuration bitstream stored in the SPI flash device and the SPI active hardware connection properly established, the SPI active configuration automatically starts after the CRESET_N signal transitions from low to high.

Table 1. Power-Up GroupsIf you are blowing the security fuses, refer to Fuse Programming Requirements.
Power-Up Sequence
Group 1	Group 2
VCC VCCA	VCCAUX VCCIO VCCIO33
MIPI D-PHY
–	VCC18A_MIPI_TX VCC18A_MIPI_RX
DDR DRAM controller
VDD_PHY VDDPLL_MCB_TOP_PHY	VDDQ_PHY VDDQX_PHY VDDQ_CK_PHY

Note: Some DDR DRAM devices have a specific power-up sequence requirement. Ensure this requirement is met when the FPGA and memory share a power supply.