Efinix, Inc.
  • Ti120 Introduction
  • Ti120 Features
    • Ti120 Package-Dependent Resources
    • Ti120 Available Package Options
  • Ti120 Device Core Functional Description
    • Ti120 XLR Cell
    • Ti120 Embedded Memory
      • Ti120 True Dual-Port Mode
      • Ti120 Simple Dual-Port Mode
    • Ti120 DSP Block
    • Ti120 Clock and Control Network
      • Ti120 Clock Sources that Drive the Global and Regional Networks
      • Ti120 Driving the Global Network
      • Ti120 Driving the Regional Network
      • Ti120 Driving the Local Network
  • Ti120 Device Interface Functional Description
    • Ti120 Interface Block Connectivity
    • Ti120 GPIO
      • Ti120 Features for HVIO and HSIO Configured as GPIO
        • Ti120 Double-Data I/O
        • Ti120 Programmable Delay Chains
      • Ti120 HVIO
      • Ti120 HSIO
        • Ti120 HSIO Configured as GPIO
        • Ti120 HSIO Configured as LVDS
        • Ti120 HSIO Configured as MIPI Lane
      • Ti120 I/O Banks
    • Ti120 DDR DRAM Interface
    • Ti120 MIPI D-PHY
      • Ti120 MIPI RX D-PHY
      • Ti120 MIPI TX D-PHY
    • Ti120 Oscillator
    • Ti120 PLL
      • Ti120 Dynamic Phase Shift
    • Ti120 Spread-Spectrum Clocking PLL
    • Ti120 Single-Event Upset Detection
    • Ti120 Internal Reconfiguration Block
  • Ti120 Security Feature
  • Ti120 Power Sequence
    • Ti120 Power-Up Sequence
    • Ti120 Power-Down Sequence
    • Ti120 Power Supply Current Transient
    • Ti120 Unused Resources and Features
  • Ti120 Configuration
    • Ti120 Supported Configuration Modes
  • Ti120 Characteristics and Timing
    • Ti120 DC and Switching Characteristics
    • Ti120 HSIO Electrical and Timing Specifications
    • Ti120 MIPI Electrical Specifications and Timing
      • Ti120 MIPI Reset Timing
    • Ti120 PLL Timing and AC Characteristics
    • Ti120 Configuration Timing
      • Ti120 JTAG Mode
      • Ti120 SPI Active Mode
      • Ti120 SPI Passive Mode
  • Ti120 Pinout Description
    • Ti120 Configuration Pins
    • Ti120 Dedicated DDR Pinout
    • Ti120 Dedicated MIPI D-PHY Pinout
    • Ti120 Pin States
  • Ti120 Interface Floorplan
  • Ti120 Efinity Software Support
  • Ti120 Ordering Codes
  • Ti120 Revision History

Ti120 Power-Down Sequence

There is no specific power-down sequence for Ti120 FPGAs. However, the VQPS power supply must follow the specifications in Fuse Programming Requirements.

Parent topic: Ti120 Power Sequence

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