Ti120 Features

  • High-density, low-power Quantum® compute fabric
  • Built on TSMC 16 nm process
  • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
  • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting
  • Versatile on-chip clocking
    • Low-skew global network supporting 32 clock or control signals
    • Regional and local clock networks
    • PLL support
  • FPGA interface blocks
    • LPDDR4/4x PHY (supporting x16 or x32 DQ widths) with memory controller hard IP
    • MIPI D-PHY hard IP with speeds up to 2.5 Gbps
    • Two varieties of general-purpose I/O (GPIO) pins:
      • High-voltage I/O (HVIO) pins support 1.8, 2.5, and 3.3 V
      • Configurable high-speed I/O (HSIO) pins support
        • Single-ended and differential I/O
        • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps
        • MIPI lane (DSI and CSI) in high-speed and low-power modes, up to 1.5 Gbps
    • PLL
    • Oscillator
    • Spread-Spectrum Clocking (SSC) PLL
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Supports internal reconfiguration
  • Single-event upset (SEU) detection feature
  • J484 packages are available in an automotive (Q3) speed grade with
    • AEC-Q100 qualification
    • Production Part Approval Process (PPAP) documentation
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1. Ti120 FPGA Resources
Logic Elements (LEs) eXchangeable Logic and Routing (XLR) Cells Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks (10 Kbits) Embedded DSP Blocks
Total SRL81
123,379 120,960 22,400 Up to 32 9.18 918 448
1 Number of XLR that can be configured as shift register with 8 maximum taps.