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T35 Introduction
T35 Features
T35 Available Package Options
T35 Device Core Functional Description
T35 XLR Cell
T35 Logic Cell
T35 Embedded Memory
T35 Multipliers
T35 Global Clock Network
T35 Clock and Control Distribution Network
T35 Global Clock Location
T35 Device Interface Functional Description
T35 Interface Block Connectivity
T35 General-Purpose I/O Logic and Buffer
T35 Complex I/O Buffer
T35 Double-Data I/O
T35 I/O Banks
T35 PLL
T35 LVDS
T35 LVDS TX
T35 LVDS RX
T35 MIPI
T35 MIPI TX
T35 MIPI TX Video Data TYPE[5:0] Settings
T35 MIPI RX
T35 MIPI RX Video Data TYPE[5:0] Settings
T35 D-PHY Timing Parameters
T35 DDR DRAM
T35 DDR Interface Designer Settings
T35 Power Up Sequence
T35 Power Supply Current Transient
T35 Unused Resources and Features
T35 Configuration
T35 Supported Configuration Modes
T35 DC and Switching Characteristics
T35 LVDS I/O Electrical and Timing Specifications
T35 ESD Performance
T35 MIPI Electrical Specifications and Timing
T35 MIPI Power-Up Timing
T35 MIPI Reset Timing
T35 PLL Timing and AC Characteristics
T35 Configuration Timing
T35 SPI Active
T35 SPI Passive
T35 JTAG
T35 Maximum tUSER for SPI Active and Passive Modes
T35 Pinout Description
T35 Pin States
T35 Efinity Software Support
T35 Interface Floorplan
T35 Ordering Codes
T35 Revision History
T35
Ordering Codes
Refer to the
Trion Selector Guide
for the full listing of
T35
ordering codes.