T35 Features

  • High-density, low-power Quantum® architecture
  • Built on SMIC 40 nm process
  • FPGA interface blocks
    • GPIO
    • PLL
    • LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs
    • MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane
    • DDR3, DDR3L, LPDDR3, LPDDR2 x16 PHY (supporting x16 DQ widths) with memory controller hard IP, up to 1066 Mbps
  • Programmable high-performance I/O
    • Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces
  • Flexible on-chip clocking
    • Low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals
    • PLL support
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Table 1. T35 FPGA Resources
LEs1 Global Clock Networks Global Control Networks Embedded Memory (kbits) Embedded Memory Blocks (5 Kbits) Embedded Multipliers
31,680 Up to 16 Up to 16 1,475 288 120
Table 2. T35 Package-Dependent Resources
Resource F256 F324 F400
Available GPIO2 191 130 230
Global clocks from GPIO pins 16 5 16
Global controls from GPIO pins 16 5 16
PLLs 7 7 7
LVDS 10 TX pairs
18 RX pairs
 20 TX pairs
26 RX pairs
 20 TX pairs
26 RX pairs
MIPI DPHY with CSI-2 controller
(4 data lanes, 1 clock lane)
 – 2 TX blocks
2 RX blocks
–
DDR3, DDR3L, LPDDR3, LPDDR2 PHY with memory controller – 1 block (x8 or x16 DQ widths) 1 block (x8 or x16 DQ widths)
Notice: Refer to the Trion Packaging User Guide for the package outlines and markings.
1 Logic capacity in equivalent LE counts.
2 The LVDS I/O pins are dual-purpose. The full number of GPIO are available when all LVDS I/O pins are in GPIO mode. GPIO and LVDS as GPIO supports different features. See Table 2.