T120 Pin States

GPIO pins have as internal pull up/down (see Figure 1), and LVDS pins used as GPIO have a weak pull up. The following table shows the pin state during reset, configuration, and when unused in user mode.

Note: For the DDR pin states, refer to the Trion DDR DRAM Block User Guide.

Table 1. I/O Pin States
Pin Type	During Reset (CRESET_N Low)	During Configuration (CRESET_N High, CDONE Low)	When Unused in User Mode (Default)
User Pins
GPIO	Input tri-state with weak pull up.	Input tri-state with weak pull up.	Input tri-state with weak pull up.¹
LVDS used as GPIO	Input tri-state with no weak pull up or pull down.	Input tri-state with no weak pull up or pull down.	Input tri-state with weak pull up.
Dual-Purpose Configuration Pins
CSO	0	0²	Input tri-state with weak pull up.
NSTATUS	1	1³	Input tri-state with weak pull up.
CCK	Input tri-state with weak pull up.	SPI active output clock. SPI passive input with weak pull up.	Input tri-state with weak pull up.
CDI0	Input tri-state with weak pull up.	SPI active output. SPI passive input with weak pull up.	Input tri-state with weak pull up.

As shown in T120 Power Up Sequence, CRESET_N must be kept low during power up.

Note: Refer to the following tables for details:

Table 8

¹ You can change it to weak pull-down in the Interface Designer.

² CSO is driven to 1 when the bitstream is done transmitting (CDONE = 1).

³ NSTATUS is driven to 0 if the FPGA detects an invalid bitstream (e.g., CRC error).