T120 Revision History

Updated CBSEL[1:0] in Table 3.

Correction to T120 MIPI Power-Up Timing.

Updated configuration timing waveforms. (DOC-2325)

Corrected MIPI reset timing diagram. (DOC-2323)

Moved information about unused resources to T120 Unused Resources and Features.

Fixed typo in Table 3. (DOC-2038)

Added note about external DC-biased circuit is required if the incoming LVDS signals are AC-coupled and link to Trion Hardware Design Checklist and Guidelines. (DOC-1532)

MIPI D-PHY specification is v1.1. (DOC-1610)

Added LVDS RX Static Mode Delay Setting. (DOC-1473)

Updated Maximum Toggle Rate table by adding recommendation to run simulation for actual toggle rate. (DOC-1468)

Updated 2.5 V and 1.8 LVCMOS Single-Ended I/O Internal Weak Pull-Up and Pull-Down Resistance. (DOC-1476)

Removed t_{LVDS_DT} and t_INDT specs, and replaced with t_{PLL_HLW} and t_{LVDS_CPA}. (DOC-1189)

Updated PLL LOCKED signal description. (DOC-1208)

Updated SPI passive X1 f_{MAX_S} specs. (DOC-1264)

Corrected t_{LVDS_SU} and t_{LVDS_HD} specs (DOC-1070)

Updated PLL RSTN signal description about de-asserting only when CLKIN is stable. (DOC-1226)

Updated t_{LVDS_skew} specs. (DOC-1111)

Updated t_{LVDS_SU} specs (DOC-1070)

Updated power up sequence diagram. (DOC-954)

Added note to use LVDS blocks from the same side to minimize skew. (DOC-1150)

Updated Advanced PLL Settings table descriptions. (DOC-945)

Added note recommending up to only 2 cascading PLLs. (DOC-931)

Corrected I_OH and I_OL in buffer drive strength characteristic specifications. (DOC-933)

Updated F_VCO, F_PLL, and F_PFD PLL Timing parameter specifications and PLL Interface Designer Settings - Manual Configuration Tab notes. (DOC-1019)

Added tLVDS_SU, tLVDS_HD specs and LVDS RX timing waveforms.

Removed PLL_EXTFB from alternative input. (DOC-849)

Updated output clock frequency for BR0 CLKOUT0 specs. (DOC-271)

Updated Advanced PLL LOCKED signal description. (DOC-763)

Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781)

Updated Connection Requirements for Unused Resources table by specifying VCC value. (DOC-770)

Updated note about leaving at least 2 pairs of unassigned LVDS pins between any GPIO and LVDS in the same device side. (DOC-769)

Updated behaviour description for GPIO and LVDS as GPIO pins during configuration, and unused GPIO pins during user mode. (DOC-720)

Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729)

Updated DDR description in features list. (DOC-733)

Updated power supply ramp rate and power up sequence diagram. (DOC-631)

Added Output Differential Voltage with Reduce VOD Swing option enabled specs. (DOC-648)

Added maximum I/O pin input current, I_IN, and maximum per bank specs. (DOC-652)

Added PLL input clock duty cycle, t_INDT, specs. (DOC-661)

Updated CDONE pin direction as bidirectional. (DOC-672)

Updated CSI pin description. (DOC-546)

Added storage temperature, T_STG spec. (DOC-560)

Updated maximum JTAG mode TCK frequency, f_TCK. (DOC-574)

Update LVDS standard compliance which is TIA/EIA-644. (DOC-592)

Updated t_CLKH and t_CLKL, and corrected SPI Passive Mode (x1) Timing Sequence waveform. (DOC-590)

Updated REF_RES_xx description. (DOC-602, DOC-605)

Updated Maximum Toggle Rate table. (DOC-630)

Updated minimum Power Supply Ramp Rates. (DOC-631)

Added note to Active mode configuration clock frequency stating that for parallel daisy chain x2 and x4 configuration, f_{MAX_M}, must be set to DIV4. (DOC-528)

Added Global Clock Location topic. (DOC-532)

Added Maximum t_USER for SPI Active and Passive Modes topic. (DOC-535)

Updated table title for Single-Ended I/O Schmitt Trigger Buffer Characteristic. (DOC-507)

Added note in Pinout Description stating all dedicated configuration pins have Schmitt Trigger buffer. (DOC-507)

Corrected total number of PLLs in PLL topic.

Updated CRESET_N pin description. (DOC-450)

Added note about limiting number of LVDS as GPIO output and bidirectional per I/O bank to avoid switching noise. (DOC-411)

Corrected floorplan diagram for F324 packages where there should only be two MIPI channels instead of three.

Added LVDS TX reference clock output duty cycle and lane-to-lane skew specs. (DOC-416)

Added information on T120S with security features.

Corrected LVDS TX Settings in Efinity® Interface Designer Output Load default value. (DOC-375)

Corrected VCC12A_MIPIxx operating conditions for C4L and I4L speed grades. (DOC-378)

Updated Density parameter description and added 256 Mb to choice to LPDDR2 in DDR Interface Designer Settings. (DOC-377)

Added I/O input voltage, V_IN specification. (DOC-389)

Added LVDS TX data and timing relationship waveform. (DOC-359)

Added LVDS RX I/O electrical specification waveform. (DOC-346)

Added data for C4L and I4L speed grades. (DOC-268)

Added a table to Power Up Sequence topic describing pin connection when PLL, GPIO, MIPI, or DDR is not used. (DOC-325)

Updated NSTATUS pin description. (DOC-335)

Updated PLL reference clock input note by asking reader to refer to PLL Timing and AC Characteristics. (DOC-336)

Added other PLL input clock frequency sources in PLL Timing and AC Characteristics. (DOC-336)

Removed OE and RST from LVDS block as they are not supported in software. (DOC-328)

For the DDR reference clock, the software issues a warning (instead of error) if you do not connect the reference clock to an I/O pad. (DOC-264)

Updated f_{MAX_S} for passive configuration modes. (DOC-350)

Updated REF_CLK description for clarity.

Updated t_USER timing parameter values and added a note about the conditions for the values.

Updated description for GPIO pins state during configuration to exclude LVDS as GPIO.

Added f_MAX for single-ended I/O and LVDS configured as single-ended I/O.

Added maximum power supply current transient during power-up.

Correct the VDDIO_DDR to VCCIO_DDR.

Removed preliminary note from DC and switching characteristics, LVDS I/O electrical specifications, MIPI electrical specifications and timing, PLL timing and AC characteristics, and configuration timing. These specifications are final.

Added VDDIO_DDR absolute maximum ratings.

Added VDDIO_DDR for DDR3, DDR3L, LPDDR3, and LPDDR2 recommended operating conditions.

Updated timing parameter symbols in boundary scan timing waveform to reflect JTAG mode parameter symbols.

Added supported GPIO features.

Updated the maximum F_VCO for PLL to 1,600 MHz.

Updated the C divider requirement for the 90 degrees phase shift in the PLL Interface Designer Settings - Manual Configuration Tab.

Updated the DDR DRAM reset signal from RST_N to CFG_RST_N.

Corrected DDR DRAM block diagram by adding DDR_CK signal.

Updated minimum setup time for passive configuration mode to 6.5ns.

Updated I/O bank names from TL_CORNER, BL_CORNER, TR_CORNER, and BR_CORNER to TL, BL, TR, and BR respectively.

Updated LVDS electrical specifications note about RX differential I/O standard support, and duplicated the note in LVDS functional description topic.

Added note to LVDS RX interface block diagram.

Removed all instances of DDR3U.

Added note to recommended power-up sequence about MIPI power guideline.

Updated the term DSP to multiplier.

Updated power up sequence description about holding CRESET_N low.

Updated PLLCLK pin name to PLL_CLKIN.

Added PLL_EXTFB and MIPI_CLKIN as an alternative input in GPIO signals table for complex I/O buffer.

Updated Memory CAS Latency (CL) choices in Advanced Options tab - Memory Mode register settings subtab.

Updated Output Drive Strength choices for LPDDR2 in Advanced Options tab - Memory Mode register settings subtab.

Corrected Enable Target 1 parameter notes in AXI 0 and AXI 1 tabs.

Removed restriction on CLKOUT1 and CLKOUT2 when CLKIN is used to drive the DDR on CLKOUT0 in DDR DRAM PHY signals table.

Added JTAG timing specifications.

Added f_MAX for DSP blocks and RAM blocks.

Added MIPI reset timing information.

VCC, VCCA, VCC12A_MIPI_TX, VCC12A_MIPI_RX maximum recommended operating condition changed to 1.25 V.

Added Trion power-up sequence. MIPI power-up moved to this topic.

Added the maximum PLL output clock speed for PLL BR0 CLKOUT0 (DDR PHY input clock).

Updated PLL Interface Designer settings.

Added PLL reference clock resource assignments.

Removed MIPI data type bit settings. Refer to AN 015: Designing with the Trion MIPI Interface for the bit settings.

Removed DIV1 and DIV2 active mode configuration frequencies; they are not supported.

Added note to LVDS electrical specifications about RX differential I/O standard support.

Added DDR pinout table.

Added waveforms for configuration timing.

Revised details for 484 pin package.

Under Ordering Codes, added link to Trion FPGA Selector Guide.