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T120 Introduction
T120 Features
T120 Available Package Options
T120 Device Core Functional Description
T120 XLR Cell
T120 Logic Cell
T120 Embedded Memory
T120 Multipliers
T120 Global Clock Network
T120 Clock and Control Distribution Network
T120 Global Clock Location
T120 Device Interface Functional Description
T120 Interface Block Connectivity
T120 General-Purpose I/O Logic and Buffer
T120 Complex I/O Buffer
T120 Double-Data I/O
T120 I/O Banks
T120 PLL
T120 LVDS
T120 LVDS TX
T120 LVDS RX
T120 MIPI
T120 MIPI TX
T120 MIPI TX Video Data TYPE[5:0] Settings
T120 MIPI RX
T120 MIPI RX Video Data TYPE[5:0] Settings
T120 D-PHY Timing Parameters
T120 DDR DRAM
T120 DDR Interface Designer Settings
T120 Power Up Sequence
T120 Power Supply Current Transient
T120 Unused Resources and Features
T120 Configuration
T120 Supported Configuration Modes
T120 DC and Switching Characteristics
T120 LVDS I/O Electrical and Timing Specifications
T120 ESD Performance
T120 MIPI Electrical Specifications and Timing
T120 MIPI Power-Up Timing
T120 MIPI Reset Timing
T120 PLL Timing and AC Characteristics
T120 Configuration Timing
T120 SPI Active
T120 SPI Passive
T120 JTAG
T120 Maximum tUSER for SPI Active and Passive Modes
T120 Pinout Description
T120 Pin States
T120 Efinity Software Support
T120 Interface Floorplan
T120 Ordering Codes
T120 Revision History
T120
Ordering Codes
Refer to the
Trion Selector Guide
for the full listing of
T120
ordering codes.