Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Location of Multiplexer Logic | Data Width | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Block | DSP Block | fMAX (MHz)1 | Efinity Version2 |
|---|---|---|---|---|---|---|---|
| Ti180 M484 C4 | High-Bandwidth and High-Performance Pipeline | ||||||
| Input | 16 | 37/172,800 (0.02%) | 0/1,280 (0%) | 0/640 (0%) | 910 | 2023.2 | |
| 64 | 133/172,800 (0.08%) | 0/1,280 (0%) | 0/640 (0%) | 840 | |||
| 256 | 517/172,800 (0.30%) | 0/1,280 (0%) | 0/640 (0%) | 650 | |||
| Output | 16 | 52/172,800 (0.03%) | 0/1,280 (0%) | 0/640 (0%) | 1050 | ||
| 64 | 196/172,800 (0.11%) | 0/1,280 (0%) | 0/640 (0%) | 1050 | |||
| 256 | 772/172,800 (0.45%) | 0/1,280 (0%) | 0/640 (0%) | 820 | |||
| Normal Pipeline | |||||||
| Input | 16 | 19/172,800 (0.01%) | 0/1,280 (0%) | 0/640 (0%) | 940 | 2023.2 | |
| 64 | 67/172,800 (0.04%) | 0/1,280 (0%) | 0/640 (0%) | 870 | |||
| 256 | 259/172,800 (0.15%) | 0/1,280 (0%) | 0/640 (0%) | 820 | |||
| Output | 16 | 19/172,800 (0.01%) | 0/1,280 (0%) | 0/640 (0%) | 940 | ||
| 64 | 67/172,800 (0.04%) | 0/1,280 (0%) | 0/640 (0%) | 870 | |||
| 256 | 259/172,800 (0.15%) | 0/1,280 (0%) | 0/640 (0%) | 820 | |||
| FPGA | Location of Multiplexer Logic | Data Width | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Block | DSP Block | fMAX (MHz)1 | Efinity Version2 |
|---|---|---|---|---|---|---|---|
| T120 F576 C4 | High-Bandwidth and High-Performance Pipeline | ||||||
| Input | 16 | 37/112,128 (0.03%) | 0/1,056 (0%) | 0/320 (0%) | 320 | 2023.2 | |
| 64 | 133/112,128 (0.12%) | 0/1,056 (0%) | 0/320 (0%) | 290 | |||
| 256 | 517/112,128 (0.46%) | 0/1,056 (0%) | 0/320 (0%) | 270 | |||
| Output | 16 | 52/112,128 (0.05%) | 0/1,056 (0%) | 0/320 (0%) | 410 | ||
| 64 | 196/112,128 (0.17%) | 0/1,056 (0%) | 0/320 (0%) | 360 | |||
| 256 | 772/112,128 (0.69%) | 0/1,056 (0%) | 0/320 (0%) | 320 | |||
| Normal Pipeline | |||||||
| Input | 16 | 19/112,128 (0.02%) | 0/1,056 (0%) | 0/320 (0%) | 300 | 2023.2 | |
| 64 | 67/112,128 (0.06%) | 0/1,056 (0%) | 0/320 (0%) | 295 | |||
| 256 | 259/112,128 (0.23%) | 0/1,056 (0%) | 0/320 (0%) | 280 | |||
| Output | 16 | 19/112,128 (0.02%) | 0/1,056 (0%) | 0/320 (0%) | 300 | ||
| 64 | 67/112,128 (0.06%) | 0/1,056 (0%) | 0/320 (0%) | 295 | |||
| 256 | 259/112,128 (0.23%) | 0/1,056 (0%) | 0/320 (0%) | 280 | |||
1 Using default
parameter settings.
2 Using Verilog
HDL.