Ports

Table 1. Clock and Reset Interface

Port	Direction	Description
clk	Input	All signals are synchronous to this clock.
resetn	Input	Synchronous reset signal that initializes all internal pointers and output flags.

Table 2. Upstream Interface

Port	Direction	Description
upstream_valid_i	Input	Indicates channel is signalling valid data.
upstream_data_i	Input	Content of data.
upstream_ready_o	Output	Logic high indicates downstream port is ready to receive the next transfer.

Table 3. Downstream Interface

Port	Direction	Description
downstream_valid_o	Input	Indicates the valid data is available.
downstream_data_o	Output	Data to be transferred.
downstream_ready_i	Input	Indicates the downstream port can accept data.