Functional Description

The Data Pipeline core is a hand-shaking mechanism where each end of a link can signal data to be sent as valid or data to be received as ready. When both ends agree (valid and ready), a data transfer occurs on that clock cycle. This mechanism is very useful when pipelining the path between a sender and a receiver for concurrency and/or timing of the data transferred.

Figure 1. Data Pipeline Core Block Diagram
The Data Pipeline core operates as follows:
  • The design is using 1 clock and 1 resetn.
  • The ready signal is registered to cut the path between input and output to ease the timing closure (for HBP = 1).
  • The downstream_data_o and downstream_valid_o are in the hold stage when downstream_ready_i is de-asserted.
  • The multiplexer introduces additional cell delay to the data path. To mitigate the timing closure, you can choose to move the multiplexer to input or output side, depending on the critical path location.
  • The Param settings are as follows:
    • HBP == 0: Normal pipeline implementation with ready back pressure.
    • HBP == 1, MUX_IN == 1: pipeline ready back pressure with multiplexer logic at input side.
    • HBP == 1, MUX_IN == 0: pipeline ready back pressure with multiplexer logic at output side.
    • D_WIDTH: data width as per design.

For Param settings with high-performance turned on, the Data Pipeline core waveform is as follows:

Figure 2. Data Pipeline Core Waveform. With high bandwidth and ready signal.

The design has the highest bandwidth performance:
  • Pointer 1—Able to take in 2 more data after the downstream_ready_i is de-asserted.
  • Pointer 2—The data in the buffer can be immediately transffered at the first positive edge when the downstream_ready_i wakes up as there is no bubble or void cycle.
Note: The timing diagram for operation of the core is similar regardless of multiplexer placement on the input or output side.

For Param settings with high-performance turned off, the Data Pipeline core waveform is as follows:

Figure 3. Data Pipeline Core Waveform. Without ready signal.

The design falls back to normal implementation where the ready signal is not in the pipeline. Maximum area saving still applies for as long as no timing closure problem emerges.