The Titanium Edge Ti125 F225 FPGA is built with enhanced high-speed I/O (HSIO2), offering exceptional flexibility for MIPI and DDR system designs and eliminating the constraints of limited hardened interfaces.
This board combines high-performance DDR3/3L memory and 128-Mbit SPI NOR flash for flexible memory and storage configurations. It also offers versatile connectivity, including dual 2.5-Gbps and 1.5-Gbps MIPI channels, a microSD card slot, and a USB 3.2 Gen 1 Type-C interface for high-speed data transfer.
This board is preloaded with an example design that demonstrates the spinning donut and running light programs by using a Sapphire SoC design with a soft-core DDR3 controller. It also displays the memory calibration status for quick verification.
With the development kit, you get a free license for the Efinity® software with 1 year of upgrades. You can request another year of maintenance for free at any time. The Efinity software provides a complete tool flow from RTL design to bitstream generation, including synthesis, place-and-route, debugging, and timing analysis.
What's in the Box
- Titanium Edge Ti125 F225 development board preloaded with a demonstration design
- 1 USB 3 Type-C to Type-C cable
- 1 USB 2.0 Type-A to Type-C cable
- 12-V, 5-A universal power adapter with 5.5-mm DC jack converter
- 4 standoffs (5 mm), 4 standoffs (10 mm), 4 screws, and 8 washers
- Jumpers
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Features
- Efinix Ti125F225C4(1) FPGA in a 225-ball FineLine BGA package
- 8-Gbit x 16 DDR3/3L memory:
- 1.5-V/1.35-V power supply
- Supports x8 width, up to 1,333 MT/s or x16 width, up to 800 MT/s
- 128-Mbit SPI NOR flash memory
- 2 high-speed QSE connectors that support up to 4 channels (4 data lanes) MIPI TX/RX interfaces or LVDS/GPIO
- 2 MIPI 2.5-Gbps 4-lane TX/RX channels(2)
- 2 MIPI 1.5-Gbps 4-lane TX/RX channels
- Micro-SD card slot
- USB 3.2 Gen 1 interface and Type-C connector
- 25-MHz, 33.33-MHz, 50-MHz, and 74.25-MHz oscillators for PLL input
- User LEDs and pushbutton switches:
- 2 power-good LEDs
- 1 NSTATUS LED
- 6 yellow LEDs on I/O banks 2A and 2B
- 3 pushbutton switches (connected to bank 3A and 3B I/O pins)
- 2 reset buttons
- Power:
- 12-V power supply connector
- On-board regulator sources: 0.95-V, 1.2-V, 1.35-V, 1.5-V, 1.8-V, 3.3-V, 5-V
- Selectable voltages for various I/O banks
(1) The FPGA speed grade may vary and is subject to availability.
(2) MIPI0 has 4 lanes for TX and RX. When MIPI1 is configured as TX, it can support up to 4 lanes. However, when configured as RX, it supports up to 2 lanes only. Refer to Table 3: QSE1 Pin Assignments in Titanium Ti125 F225 Development Kit User Guide for pinout details.
Titanium Edge Ti125 F225 Development Board
Titanium Edge Ti125 F225 Board Block Diagram
Titanium Edge Ti125 F225 Development Kit Contents
Resources
Example Designs